mfd: Add Rockchip rk817 audio CODEC support

Add rk817 codec support cell to rk808 mfd driver.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index ad923dd..77ccd31 100644 (file)
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -65,6 +65,7 @@ static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
        switch (reg) {
        case RK817_SECONDS_REG ... RK817_WEEKS_REG:
        case RK817_RTC_STATUS_REG:
+       case RK817_CODEC_DTOP_LPT_SRST:
        case RK817_INT_STS_REG0:
        case RK817_INT_STS_REG1:
        case RK817_INT_STS_REG2:
@@ -163,6 +164,7 @@ static const struct mfd_cell rk817s[] = {
                .num_resources = ARRAY_SIZE(rk817_rtc_resources),
                .resources = &rk817_rtc_resources[0],
        },
+       { .name = "rk817-codec",},
 };
 
 static const struct mfd_cell rk818s[] = {
@@ -201,6 +203,85 @@ static const struct rk808_reg_data rk808_pre_init_reg[] = {
 
 static const struct rk808_reg_data rk817_pre_init_reg[] = {
        {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
+       /* Codec specific registers */
+       { RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
+       { RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
+       { RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
+       { RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
+       /* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
+       { RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
+       { RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
+       { RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
+       /* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
+       { RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
+       { RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
+       { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
+       { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
+       { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
+       { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
+       /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
+       { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
+       { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
+       { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
+       { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
+       { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
+       { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
+       { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
+       { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
+       { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
+       /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
+       { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
+       { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
+       { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
+       { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
+       { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
+       { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
+       { RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
+       { RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
+       { RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
+       { RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
+       { RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
+       { RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
+       { RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
+       { RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
+       { RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
+       { RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
+       { RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
+       { RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
+       { RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
+       { RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
+       { RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
+       { RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
+       { RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
+       { RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
+       { RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
+       { RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
+       { RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
        {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
        {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
                                           RK817_HOTDIE_105 | RK817_TSD_140},

diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index e07f6e6..a96e6d4 100644 (file)
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -437,6 +437,87 @@ enum rk809_reg_id {
 #define RK817_RTC_COMP_LSB_REG         0x10
 #define RK817_RTC_COMP_MSB_REG         0x11
 
+/* RK817 Codec Registers */
+#define RK817_CODEC_DTOP_VUCTL         0x12
+#define RK817_CODEC_DTOP_VUCTIME       0x13
+#define RK817_CODEC_DTOP_LPT_SRST      0x14
+#define RK817_CODEC_DTOP_DIGEN_CLKE    0x15
+#define RK817_CODEC_AREF_RTCFG0                0x16
+#define RK817_CODEC_AREF_RTCFG1                0x17
+#define RK817_CODEC_AADC_CFG0          0x18
+#define RK817_CODEC_AADC_CFG1          0x19
+#define RK817_CODEC_DADC_VOLL          0x1a
+#define RK817_CODEC_DADC_VOLR          0x1b
+#define RK817_CODEC_DADC_SR_ACL0       0x1e
+#define RK817_CODEC_DADC_ALC1          0x1f
+#define RK817_CODEC_DADC_ALC2          0x20
+#define RK817_CODEC_DADC_NG            0x21
+#define RK817_CODEC_DADC_HPF           0x22
+#define RK817_CODEC_DADC_RVOLL         0x23
+#define RK817_CODEC_DADC_RVOLR         0x24
+#define RK817_CODEC_AMIC_CFG0          0x27
+#define RK817_CODEC_AMIC_CFG1          0x28
+#define RK817_CODEC_DMIC_PGA_GAIN      0x29
+#define RK817_CODEC_DMIC_LMT1          0x2a
+#define RK817_CODEC_DMIC_LMT2          0x2b
+#define RK817_CODEC_DMIC_NG1           0x2c
+#define RK817_CODEC_DMIC_NG2           0x2d
+#define RK817_CODEC_ADAC_CFG0          0x2e
+#define RK817_CODEC_ADAC_CFG1          0x2f
+#define RK817_CODEC_DDAC_POPD_DACST    0x30
+#define RK817_CODEC_DDAC_VOLL          0x31
+#define RK817_CODEC_DDAC_VOLR          0x32
+#define RK817_CODEC_DDAC_SR_LMT0       0x35
+#define RK817_CODEC_DDAC_LMT1          0x36
+#define RK817_CODEC_DDAC_LMT2          0x37
+#define RK817_CODEC_DDAC_MUTE_MIXCTL   0x38
+#define RK817_CODEC_DDAC_RVOLL         0x39
+#define RK817_CODEC_DDAC_RVOLR         0x3a
+#define RK817_CODEC_AHP_ANTI0          0x3b
+#define RK817_CODEC_AHP_ANTI1          0x3c
+#define RK817_CODEC_AHP_CFG0           0x3d
+#define RK817_CODEC_AHP_CFG1           0x3e
+#define RK817_CODEC_AHP_CP             0x3f
+#define RK817_CODEC_ACLASSD_CFG1       0x40
+#define RK817_CODEC_ACLASSD_CFG2       0x41
+#define RK817_CODEC_APLL_CFG0          0x42
+#define RK817_CODEC_APLL_CFG1          0x43
+#define RK817_CODEC_APLL_CFG2          0x44
+#define RK817_CODEC_APLL_CFG3          0x45
+#define RK817_CODEC_APLL_CFG4          0x46
+#define RK817_CODEC_APLL_CFG5          0x47
+#define RK817_CODEC_DI2S_CKM           0x48
+#define RK817_CODEC_DI2S_RSD           0x49
+#define RK817_CODEC_DI2S_RXCR1         0x4a
+#define RK817_CODEC_DI2S_RXCR2         0x4b
+#define RK817_CODEC_DI2S_RXCMD_TSD     0x4c
+#define RK817_CODEC_DI2S_TXCR1         0x4d
+#define RK817_CODEC_DI2S_TXCR2         0x4e
+#define RK817_CODEC_DI2S_TXCR3_TXCMD   0x4f
+
+/* RK817_CODEC_DI2S_CKM */
+#define RK817_I2S_MODE_MASK            (0x1 << 0)
+#define RK817_I2S_MODE_MST             (0x1 << 0)
+#define RK817_I2S_MODE_SLV             (0x0 << 0)
+
+/* RK817_CODEC_DDAC_MUTE_MIXCTL */
+#define DACMT_MASK                     (0x1 << 0)
+#define DACMT_ENABLE                   (0x1 << 0)
+#define DACMT_DISABLE                  (0x0 << 0)
+
+/* RK817_CODEC_DI2S_RXCR2 */
+#define VDW_RX_24BITS                  (0x17)
+#define VDW_RX_16BITS                  (0x0f)
+
+/* RK817_CODEC_DI2S_TXCR2 */
+#define VDW_TX_24BITS                  (0x17)
+#define VDW_TX_16BITS                  (0x0f)
+
+/* RK817_CODEC_AMIC_CFG0 */
+#define MIC_DIFF_MASK                  (0x1 << 7)
+#define MIC_DIFF_DIS                   (0x0 << 7)
+#define MIC_DIFF_EN                    (0x1 << 7)
+
 #define RK817_POWER_EN_REG(i)          (0xb1 + (i))
 #define RK817_POWER_SLP_EN_REG(i)      (0xb5 + (i))