drm/amd/display: enable hdmistreamclk_rcg by default for dcn42

[why]
enable hdmistreamclk_rcg by default

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 617f504..5c9ef30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1680,8 +1680,11 @@ void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-       if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream)
-               REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0);
+       if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream && !enable) {
+               DC_LOG_DEBUG("%s: HDMISTREAMCLK0_ROOT_GATE DISABLE = 0 bypassed", __func__);
+               return;
+       }
+       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0);
 
        DC_LOG_DEBUG("%s: HDMISTREAMCLK0_ROOT_GATE_DISABLE = %d\n", __func__, enable ? 1 : 0);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 01027d1..f14c39a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -487,7 +487,7 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 
 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
 {
-       if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
+       if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp && !clock_on)
                return;
 
        if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {
@@ -498,7 +498,7 @@ void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst,
 
 void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on)
 {
-       if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+       if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpstream && !clock_on)
                return;
 
        if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {
@@ -509,7 +509,7 @@ void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hp
 
 void dcn35_hdmistream_root_clock_control(struct dce_hwseq *hws, bool clock_on)
 {
-       if (!hws->ctx->dc->debug.root_clock_optimization.bits.hdmistream)
+       if (!hws->ctx->dc->debug.root_clock_optimization.bits.hdmistream && !clock_on)
                return;
 
        if (hws->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk_root_clock_gating) {
@@ -520,7 +520,7 @@ void dcn35_hdmistream_root_clock_control(struct dce_hwseq *hws, bool clock_on)
 
 void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)
 {
-       if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+       if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk && !clock_on)
                return;
 
        if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 7620da9..640a5a4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -762,7 +762,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                .bits = {
                        .dpp = true,
                        .dsc = true,/*dscclk and dsc pg*/
-                       .hdmistream = false,
+                       .hdmistream = true,
                        .hdmichar = true,
                        .dpstream = true,
                        .symclk32_se = true,