Merge tag 'renesas-r8a779a0-dt-binding-defs-tag' into renesas-drivers-for-v5.10

Renesas R-Car V3U DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car V3U (R8A779A0)
SoC, shared by driver and DT source files.

diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
new file mode 100644 (file)
index 0000000..f1d737c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779A0 CPG Core Clocks */
+#define R8A779A0_CLK_Z0                        0
+#define R8A779A0_CLK_ZX                        1
+#define R8A779A0_CLK_Z1                        2
+#define R8A779A0_CLK_ZR                        3
+#define R8A779A0_CLK_ZS                        4
+#define R8A779A0_CLK_ZT                        5
+#define R8A779A0_CLK_ZTR               6
+#define R8A779A0_CLK_S1D1              7
+#define R8A779A0_CLK_S1D2              8
+#define R8A779A0_CLK_S1D4              9
+#define R8A779A0_CLK_S1D8              10
+#define R8A779A0_CLK_S1D12             11
+#define R8A779A0_CLK_S3D1              12
+#define R8A779A0_CLK_S3D2              13
+#define R8A779A0_CLK_S3D4              14
+#define R8A779A0_CLK_LB                        15
+#define R8A779A0_CLK_CP                        16
+#define R8A779A0_CLK_CL                        17
+#define R8A779A0_CLK_CL16MCK           18
+#define R8A779A0_CLK_ZB30              19
+#define R8A779A0_CLK_ZB30D2            20
+#define R8A779A0_CLK_ZB30D4            21
+#define R8A779A0_CLK_ZB31              22
+#define R8A779A0_CLK_ZB31D2            23
+#define R8A779A0_CLK_ZB31D4            24
+#define R8A779A0_CLK_SD0H              25
+#define R8A779A0_CLK_SD0               26
+#define R8A779A0_CLK_RPC               27
+#define R8A779A0_CLK_RPCD2             28
+#define R8A779A0_CLK_MSO               29
+#define R8A779A0_CLK_CANFD             30
+#define R8A779A0_CLK_CSI0              31
+#define R8A779A0_CLK_FRAY              32
+#define R8A779A0_CLK_DSI               33
+#define R8A779A0_CLK_VIP               34
+#define R8A779A0_CLK_ADGH              35
+#define R8A779A0_CLK_CNNDSP            36
+#define R8A779A0_CLK_ICU               37
+#define R8A779A0_CLK_ICUD2             38
+#define R8A779A0_CLK_VCBUS             39
+#define R8A779A0_CLK_CBFUSA            40
+#define R8A779A0_CLK_R                 41
+#define R8A779A0_CLK_OSC               42
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h
new file mode 100644 (file)
index 0000000..57929e4
--- /dev/null
+++ b/include/dt-bindings/power/r8a779a0-sysc.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779A0_PD_A1E0D0C0           0
+#define R8A779A0_PD_A1E0D0C1           1
+#define R8A779A0_PD_A1E0D1C0           2
+#define R8A779A0_PD_A1E0D1C1           3
+#define R8A779A0_PD_A1E1D0C0           4
+#define R8A779A0_PD_A1E1D0C1           5
+#define R8A779A0_PD_A1E1D1C0           6
+#define R8A779A0_PD_A1E1D1C1           7
+#define R8A779A0_PD_A2E0D0             16
+#define R8A779A0_PD_A2E0D1             17
+#define R8A779A0_PD_A2E1D0             18
+#define R8A779A0_PD_A2E1D1             19
+#define R8A779A0_PD_A3E0               20
+#define R8A779A0_PD_A3E1               21
+#define R8A779A0_PD_3DG_A              24
+#define R8A779A0_PD_3DG_B              25
+#define R8A779A0_PD_A1CNN2             32
+#define R8A779A0_PD_A1DSP0             33
+#define R8A779A0_PD_A2IMP01            34
+#define R8A779A0_PD_A2DP0              35
+#define R8A779A0_PD_A2CV0              36
+#define R8A779A0_PD_A2CV1              37
+#define R8A779A0_PD_A2CV4              38
+#define R8A779A0_PD_A2CV6              39
+#define R8A779A0_PD_A2CN2              40
+#define R8A779A0_PD_A1CNN0             41
+#define R8A779A0_PD_A2CN0              42
+#define R8A779A0_PD_A3IR               43
+#define R8A779A0_PD_A1CNN1             44
+#define R8A779A0_PD_A1DSP1             45
+#define R8A779A0_PD_A2IMP23            46
+#define R8A779A0_PD_A2DP1              47
+#define R8A779A0_PD_A2CV2              48
+#define R8A779A0_PD_A2CV3              49
+#define R8A779A0_PD_A2CV5              50
+#define R8A779A0_PD_A2CV7              51
+#define R8A779A0_PD_A2CN1              52
+#define R8A779A0_PD_A3VIP0             56
+#define R8A779A0_PD_A3VIP1             57
+#define R8A779A0_PD_A3VIP2             58
+#define R8A779A0_PD_A3VIP3             59
+#define R8A779A0_PD_A3ISP01            60
+#define R8A779A0_PD_A3ISP23            61
+
+/* Always-on power area */
+#define R8A779A0_PD_ALWAYS_ON          64
+
+#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */