MIPS: Convert R4600_V2_HIT_CACHEOP into a config option

Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 714cd81..e4198c5 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -640,6 +640,7 @@ config SGI_IP22
        select SYS_SUPPORTS_BIG_ENDIAN
        select WAR_R4600_V1_INDEX_ICACHEOP
        select WAR_R4600_V1_HIT_CACHEOP
+       select WAR_R4600_V2_HIT_CACHEOP
        select MIPS_L1_CACHE_SHIFT_7
        help
          This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -877,6 +878,7 @@ config SNI_RM
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_SUPPORTS_LITTLE_ENDIAN
+       select WAR_R4600_V2_HIT_CACHEOP
        help
          The SNI RM200/300/400 are MIPS-based machines manufactured by
          Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP
 config WAR_R4600_V1_HIT_CACHEOP
        bool
 
+# Writeback and invalidate the primary cache dcache before DMA.
+#
+# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
+# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
+# operate correctly if the internal data cache refill buffer is empty.  These
+# CACHE instructions should be separated from any potential data cache miss
+# by a load instruction to an uncached address to empty the response buffer."
+# (Revision 2.0 device errata from IDT available on https://www.idt.com/
+# in .pdf format.)
+config WAR_R4600_V2_HIT_CACHEOP
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 915ce03..4bc396d 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
 #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 44d14be..4d46a88 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_WAR_H
 #define __ASM_MACH_GENERIC_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 9154c54..a5a1c41 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -8,11 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP22_WAR_H
 #define __ASM_MIPS_MACH_IP22_WAR_H
 
-/*
- * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e7c070c..5891d50 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP27_WAR_H
 #define __ASM_MIPS_MACH_IP27_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 22d9f78..346fc56 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP28_WAR_H
 #define __ASM_MIPS_MACH_IP28_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 1400b03..f887a0a 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_MIPS_MACH_IP30_WAR_H
 #define __ASM_MIPS_MACH_IP30_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index f91f4ed..980dbd3 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP32_WAR_H
 #define __ASM_MIPS_MACH_IP32_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index a4d5d09..29f5680 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 82ce2d3..749787b 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 192ec33..aded634 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -8,11 +8,6 @@
 #ifndef __ASM_MIPS_MACH_RM_WAR_H
 #define __ASM_MIPS_MACH_RM_WAR_H
 
-/*
- * The RM200C seems to have been shipped only with V2.0 R4600s
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index bf793d3..78fd2ad 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,8 +8,6 @@
 #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
 #define __ASM_MIPS_MACH_SIBYTE_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
-
 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
 
 #ifndef __ASSEMBLY__

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7da1a3e..0b1666e 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
 #define __ASM_MIPS_MACH_TX49XX_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d336a0e..37092c2 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,21 +72,6 @@
 #define DADDI_WAR 0
 #endif
 
-/*
- * Writeback and invalidate the primary cache dcache before DMA.
- *
- * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
- * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
- * operate correctly if the internal data cache refill buffer is empty.         These
- * CACHE instructions should be separated from any potential data cache miss
- * by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on https://www.idt.com/
- * in .pdf format.)
- */
-#ifndef R4600_V2_HIT_CACHEOP_WAR
-#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
-#endif
-
 /*
  * Workaround for the Sibyte M3 errata the text of which can be found at
  *

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 814a295..df09a36 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -130,7 +130,8 @@ struct bcache_ops *bcops = &no_sc_ops;
 
 #define R4600_HIT_CACHEOP_WAR_IMPL                                     \
 do {                                                                   \
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&              \
+           cpu_is_r4600_v2_x())                                        \
                *(volatile unsigned long *)CKSEG1;                      \
        if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP))                                        \
                __asm__ __volatile__("nop;nop;nop;nop");                \

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index ecad11f..504bc40 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -258,7 +258,8 @@ static inline void build_clear_pref(u32 **buf, int off)
                                uasm_i_nop(buf);
                        }
 
-                       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+                           cpu_is_r4600_v2_x())
                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -303,7 +304,7 @@ void build_clear_page(void)
        else
                uasm_i_ori(&buf, A2, A0, off);
 
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
        off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
@@ -411,7 +412,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
                                uasm_i_nop(buf);
                        }
 
-                       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+                           cpu_is_r4600_v2_x())
                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -455,7 +457,7 @@ void build_copy_page(void)
        else
                uasm_i_ori(&buf, A2, A0, off);
 
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
        off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *