}
clk_mgr->base.base.dprefclk_khz = 600000;
- clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
+ clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
+ clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
dce_clock_read_ss_info(&clk_mgr->base);
+ clk_mgr->base.dccg->ref_dtbclk_khz =
+ dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
clk_mgr->base.base.bw_params = &dcn316_bw_params;
VBIOSSMC_MSG_SetDtbclkFreq,
enable);
}
+
+int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)
+{
+ int dprefclk_get_mhz = -1;
+
+ if (clk_mgr->smu_present) {
+ dprefclk_get_mhz = dcn316_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_GetDprefclkFreq,
+ 0);
+ }
+ return (dprefclk_get_mhz * 1000);
+}
+
+int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr)
+{
+ int fclk_get_mhz = -1;
+
+ if (clk_mgr->smu_present) {
+ fclk_get_mhz = dcn316_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_GetFclkFrequency,
+ 0);
+ }
+ return (fclk_get_mhz * 1000);
+}
void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
+int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
+int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_316_SMU_H_ */