gpio: hlwd: use new generic GPIO chip API

Convert the driver to using the new generic GPIO chip interfaces from
linux/gpio/generic.h.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-3-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c
index 0580f67..a395f87 100644 (file)
--- a/drivers/gpio/gpio-hlwd.c
+++ b/drivers/gpio/gpio-hlwd.c
@@ -6,6 +6,7 @@
 // Nintendo Wii (Hollywood) GPIO driver
 
 #include <linux/gpio/driver.h>
+#include <linux/gpio/generic.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -48,7 +49,7 @@
 #define HW_GPIO_OWNER          0x3c
 
 struct hlwd_gpio {
-       struct gpio_chip gpioc;
+       struct gpio_generic_chip gpioc;
        struct device *dev;
        void __iomem *regs;
        int irq;
@@ -61,45 +62,44 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc)
        struct hlwd_gpio *hlwd =
                gpiochip_get_data(irq_desc_get_handler_data(desc));
        struct irq_chip *chip = irq_desc_get_chip(desc);
-       unsigned long flags;
        unsigned long pending;
        int hwirq;
        u32 emulated_pending;
 
-       raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
-       pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
-       pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
+       scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
+               pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
+               pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
 
-       /* Treat interrupts due to edge trigger emulation separately */
-       emulated_pending = hlwd->edge_emulation & pending;
-       pending &= ~emulated_pending;
-       if (emulated_pending) {
-               u32 level, rising, falling;
+               /* Treat interrupts due to edge trigger emulation separately */
+               emulated_pending = hlwd->edge_emulation & pending;
+               pending &= ~emulated_pending;
+               if (emulated_pending) {
+                       u32 level, rising, falling;
 
-               level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
-               rising = level & emulated_pending;
-               falling = ~level & emulated_pending;
+                       level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
+                       rising = level & emulated_pending;
+                       falling = ~level & emulated_pending;
 
-               /* Invert the levels */
-               iowrite32be(level ^ emulated_pending,
-                           hlwd->regs + HW_GPIOB_INTLVL);
+                       /* Invert the levels */
+                       iowrite32be(level ^ emulated_pending,
+                                   hlwd->regs + HW_GPIOB_INTLVL);
 
-               /* Ack all emulated-edge interrupts */
-               iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
+                       /* Ack all emulated-edge interrupts */
+                       iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
 
-               /* Signal interrupts only on the correct edge */
-               rising &= hlwd->rising_edge;
-               falling &= hlwd->falling_edge;
+                       /* Signal interrupts only on the correct edge */
+                       rising &= hlwd->rising_edge;
+                       falling &= hlwd->falling_edge;
 
-               /* Mark emulated interrupts as pending */
-               pending |= rising | falling;
+                       /* Mark emulated interrupts as pending */
+                       pending |= rising | falling;
+               }
        }
-       raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
 
        chained_irq_enter(chip, desc);
 
        for_each_set_bit(hwirq, &pending, 32)
-               generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
+               generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq);
 
        chained_irq_exit(chip, desc);
 }
@@ -116,30 +116,29 @@ static void hlwd_gpio_irq_mask(struct irq_data *data)
 {
        struct hlwd_gpio *hlwd =
                gpiochip_get_data(irq_data_get_irq_chip_data(data));
-       unsigned long flags;
        u32 mask;
 
-       raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
-       mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
-       mask &= ~BIT(data->hwirq);
-       iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
-       raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
-       gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
+       scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
+               mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
+               mask &= ~BIT(data->hwirq);
+               iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
+       }
+       gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
 }
 
 static void hlwd_gpio_irq_unmask(struct irq_data *data)
 {
        struct hlwd_gpio *hlwd =
                gpiochip_get_data(irq_data_get_irq_chip_data(data));
-       unsigned long flags;
        u32 mask;
 
-       gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
-       raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+       gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
+
+       guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
+
        mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
        mask |= BIT(data->hwirq);
        iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
-       raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
 }
 
 static void hlwd_gpio_irq_enable(struct irq_data *data)
@@ -173,10 +172,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
 {
        struct hlwd_gpio *hlwd =
                gpiochip_get_data(irq_data_get_irq_chip_data(data));
-       unsigned long flags;
        u32 level;
 
-       raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+       guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
 
        hlwd->edge_emulation &= ~BIT(data->hwirq);
 
@@ -197,11 +195,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
                hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
                break;
        default:
-               raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
                return -EINVAL;
        }
 
-       raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
        return 0;
 }
 
@@ -225,6 +221,7 @@ static const struct irq_chip hlwd_gpio_irq_chip = {
 
 static int hlwd_gpio_probe(struct platform_device *pdev)
 {
+       struct gpio_generic_chip_config config;
        struct hlwd_gpio *hlwd;
        u32 ngpios;
        int res;
@@ -244,25 +241,31 @@ static int hlwd_gpio_probe(struct platform_device *pdev)
         * systems where the AHBPROT memory firewall hasn't been configured to
         * permit PPC access to HW_GPIO_*.
         *
-        * Note that this has to happen before bgpio_init reads the
-        * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
-        * values.
+        * Note that this has to happen before gpio_generic_chip_init() reads
+        * the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the
+        * wrong values.
         */
        iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
 
-       res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
-                       hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
-                       NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
-                       BGPIOF_BIG_ENDIAN_BYTE_ORDER);
+       config = (struct gpio_generic_chip_config) {
+               .dev = &pdev->dev,
+               .sz = 4,
+               .dat = hlwd->regs + HW_GPIOB_IN,
+               .set = hlwd->regs + HW_GPIOB_OUT,
+               .dirout = hlwd->regs + HW_GPIOB_DIR,
+               .flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
+       };
+
+       res = gpio_generic_chip_init(&hlwd->gpioc, &config);
        if (res < 0) {
-               dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
+               dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res);
                return res;
        }
 
        res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
        if (res)
                ngpios = 32;
-       hlwd->gpioc.ngpio = ngpios;
+       hlwd->gpioc.gc.ngpio = ngpios;
 
        /* Mask and ack all interrupts */
        iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
@@ -282,7 +285,7 @@ static int hlwd_gpio_probe(struct platform_device *pdev)
                        return hlwd->irq;
                }
 
-               girq = &hlwd->gpioc.irq;
+               girq = &hlwd->gpioc.gc.irq;
                gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip);
                girq->parent_handler = hlwd_gpio_irqhandler;
                girq->num_parents = 1;
@@ -296,7 +299,7 @@ static int hlwd_gpio_probe(struct platform_device *pdev)
                girq->handler = handle_level_irq;
        }
 
-       return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
+       return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc.gc, hlwd);
 }
 
 static const struct of_device_id hlwd_gpio_match[] = {