clk: imx8mp: add clkout1/2 support

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c8a0534..ba058fb 100644 (file)
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au
 
 static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
 
+static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+                                                 "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
+                                                 "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+                                                 "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw **hws;
 static struct clk_hw_onecell_data *clk_hw_data;
 
@@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
        hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
        hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+       hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4,
+                                                     imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
+       hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4);
+       hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8);
+       hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4,
+                                                     imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
+       hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
+       hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
+
        hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
        hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
        hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];

diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index e05d21b..9d5cc2d 100644 (file)
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -317,10 +317,15 @@
 #define IMX8MP_CLK_AUDIO_AXI                   310
 #define IMX8MP_CLK_HSIO_AXI                    311
 #define IMX8MP_CLK_MEDIA_ISP                   312
-
 #define IMX8MP_CLK_MEDIA_DISP2_PIX             313
+#define IMX8MP_CLK_CLKOUT1_SEL                 314
+#define IMX8MP_CLK_CLKOUT1_DIV                 315
+#define IMX8MP_CLK_CLKOUT1                     316
+#define IMX8MP_CLK_CLKOUT2_SEL                 317
+#define IMX8MP_CLK_CLKOUT2_DIV                 318
+#define IMX8MP_CLK_CLKOUT2                     319
 
-#define IMX8MP_CLK_END                         314
+#define IMX8MP_CLK_END                         320
 
 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG           0
 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1         1