F: include/linux/kobj*
F: lib/kobj*
-DRIVERS FOR ADAPTIVE VOLTAGE SCALING (AVS)
+DRIVERS FOR OMAP ADAPTIVE VOLTAGE SCALING (AVS)
M: Nishanth Menon <nm@ti.com>
L: linux-pm@vger.kernel.org
S: Maintained
-F: drivers/power/avs/
+F: drivers/soc/ti/smartreflex.c
F: include/linux/power/smartreflex.h
DRM DRIVER FOR ALLWINNER DE2 AND DE3 ENGINE
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
-F: drivers/power/avs/qcom-cpr.c
+F: drivers/soc/qcom/cpr.c
QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
M: Ilia Lin <ilia.lin@kernel.org>
config POWER_AVS_OMAP
bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
- depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
+ depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
select POWER_SUPPLY
help
Say Y to enable AVS(Adaptive Voltage Scaling)
# SPDX-License-Identifier: GPL-2.0-only
-source "drivers/power/avs/Kconfig"
source "drivers/power/reset/Kconfig"
source "drivers/power/supply/Kconfig"
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_POWER_AVS) += avs/
obj-$(CONFIG_POWER_RESET) += reset/
obj-$(CONFIG_POWER_SUPPLY) += supply/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig POWER_AVS
- bool "Adaptive Voltage Scaling class support"
- help
- AVS is a power management technique which finely controls the
- operating voltage of a device in order to optimize (i.e. reduce)
- its power consumption.
- At a given operating point the voltage is adapted depending on
- static factors (chip manufacturing process) and dynamic factors
- (temperature depending performance).
- AVS is also called SmartReflex on OMAP devices.
-
- Say Y here to enable Adaptive Voltage Scaling class support.
-
-config QCOM_CPR
- tristate "QCOM Core Power Reduction (CPR) support"
- depends on POWER_AVS && HAS_IOMEM
- select PM_OPP
- select REGMAP
- help
- Say Y here to enable support for the CPR hardware found on Qualcomm
- SoCs like QCS404.
-
- This driver populates CPU OPPs tables and makes adjustments to the
- tables based on feedback from the CPR hardware. If you want to do
- CPUfrequency scaling say Y here.
-
- To compile this driver as a module, choose M here: the module will
- be called qcom-cpr
-
-config ROCKCHIP_IODOMAIN
- tristate "Rockchip IO domain support"
- depends on POWER_AVS && ARCH_ROCKCHIP && OF
- help
- Say y here to enable support io domains on Rockchip SoCs. It is
- necessary for the io domain setting of the SoC to match the
- voltage supplied by the regulators.
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_POWER_AVS_OMAP) += smartreflex.o
-obj-$(CONFIG_QCOM_CPR) += qcom-cpr.o
-obj-$(CONFIG_ROCKCHIP_IODOMAIN) += rockchip-io-domain.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Linaro Limited
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/debugfs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_opp.h>
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regulator/consumer.h>
-#include <linux/clk.h>
-#include <linux/nvmem-consumer.h>
-
-/* Register Offsets for RB-CPR and Bit Definitions */
-
-/* RBCPR Version Register */
-#define REG_RBCPR_VERSION 0
-#define RBCPR_VER_2 0x02
-#define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0)
-
-/* RBCPR Gate Count and Target Registers */
-#define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n))
-
-#define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
-#define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)
-#define RBCPR_GCNT_TARGET_GCNT_SHIFT 12
-#define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)
-
-/* RBCPR Timer Control */
-#define REG_RBCPR_TIMER_INTERVAL 0x44
-#define REG_RBIF_TIMER_ADJUST 0x4c
-
-#define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)
-#define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0
-#define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)
-#define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
-#define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)
-#define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
-
-/* RBCPR Config Register */
-#define REG_RBIF_LIMIT 0x48
-#define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)
-#define RBIF_LIMIT_CEILING_SHIFT 6
-#define RBIF_LIMIT_FLOOR_BITS 6
-#define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)
-
-#define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK
-#define RBIF_LIMIT_FLOOR_DEFAULT 0
-
-#define REG_RBIF_SW_VLEVEL 0x94
-#define RBIF_SW_VLEVEL_DEFAULT 0x20
-
-#define REG_RBCPR_STEP_QUOT 0x80
-#define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)
-#define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)
-#define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
-
-/* RBCPR Control Register */
-#define REG_RBCPR_CTL 0x90
-
-#define RBCPR_CTL_LOOP_EN BIT(0)
-#define RBCPR_CTL_TIMER_EN BIT(3)
-#define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5)
-#define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6)
-#define RBCPR_CTL_COUNT_MODE BIT(10)
-#define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)
-#define RBCPR_CTL_UP_THRESHOLD_SHIFT 24
-#define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)
-#define RBCPR_CTL_DN_THRESHOLD_SHIFT 28
-
-/* RBCPR Ack/Nack Response */
-#define REG_RBIF_CONT_ACK_CMD 0x98
-#define REG_RBIF_CONT_NACK_CMD 0x9c
-
-/* RBCPR Result status Register */
-#define REG_RBCPR_RESULT_0 0xa0
-
-#define RBCPR_RESULT0_BUSY_SHIFT 19
-#define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT)
-#define RBCPR_RESULT0_ERROR_LT0_SHIFT 18
-#define RBCPR_RESULT0_ERROR_SHIFT 6
-#define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)
-#define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
-#define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
-#define RBCPR_RESULT0_STEP_UP_SHIFT 1
-
-/* RBCPR Interrupt Control Register */
-#define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n))
-#define REG_RBIF_IRQ_CLEAR 0x110
-#define REG_RBIF_IRQ_STATUS 0x114
-
-#define CPR_INT_DONE BIT(0)
-#define CPR_INT_MIN BIT(1)
-#define CPR_INT_DOWN BIT(2)
-#define CPR_INT_MID BIT(3)
-#define CPR_INT_UP BIT(4)
-#define CPR_INT_MAX BIT(5)
-#define CPR_INT_CLAMP BIT(6)
-#define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
- CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
-#define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
-
-#define CPR_NUM_RING_OSC 8
-
-/* CPR eFuse parameters */
-#define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
-
-#define CPR_FUSE_MIN_QUOT_DIFF 50
-
-#define FUSE_REVISION_UNKNOWN (-1)
-
-enum voltage_change_dir {
- NO_CHANGE,
- DOWN,
- UP,
-};
-
-struct cpr_fuse {
- char *ring_osc;
- char *init_voltage;
- char *quotient;
- char *quotient_offset;
-};
-
-struct fuse_corner_data {
- int ref_uV;
- int max_uV;
- int min_uV;
- int max_volt_scale;
- int max_quot_scale;
- /* fuse quot */
- int quot_offset;
- int quot_scale;
- int quot_adjust;
- /* fuse quot_offset */
- int quot_offset_scale;
- int quot_offset_adjust;
-};
-
-struct cpr_fuses {
- int init_voltage_step;
- int init_voltage_width;
- struct fuse_corner_data *fuse_corner_data;
-};
-
-struct corner_data {
- unsigned int fuse_corner;
- unsigned long freq;
-};
-
-struct cpr_desc {
- unsigned int num_fuse_corners;
- int min_diff_quot;
- int *step_quot;
-
- unsigned int timer_delay_us;
- unsigned int timer_cons_up;
- unsigned int timer_cons_down;
- unsigned int up_threshold;
- unsigned int down_threshold;
- unsigned int idle_clocks;
- unsigned int gcnt_us;
- unsigned int vdd_apc_step_up_limit;
- unsigned int vdd_apc_step_down_limit;
- unsigned int clamp_timer_interval;
-
- struct cpr_fuses cpr_fuses;
- bool reduce_to_fuse_uV;
- bool reduce_to_corner_uV;
-};
-
-struct acc_desc {
- unsigned int enable_reg;
- u32 enable_mask;
-
- struct reg_sequence *config;
- struct reg_sequence *settings;
- int num_regs_per_fuse;
-};
-
-struct cpr_acc_desc {
- const struct cpr_desc *cpr_desc;
- const struct acc_desc *acc_desc;
-};
-
-struct fuse_corner {
- int min_uV;
- int max_uV;
- int uV;
- int quot;
- int step_quot;
- const struct reg_sequence *accs;
- int num_accs;
- unsigned long max_freq;
- u8 ring_osc_idx;
-};
-
-struct corner {
- int min_uV;
- int max_uV;
- int uV;
- int last_uV;
- int quot_adjust;
- u32 save_ctl;
- u32 save_irq;
- unsigned long freq;
- struct fuse_corner *fuse_corner;
-};
-
-struct cpr_drv {
- unsigned int num_corners;
- unsigned int ref_clk_khz;
-
- struct generic_pm_domain pd;
- struct device *dev;
- struct device *attached_cpu_dev;
- struct mutex lock;
- void __iomem *base;
- struct corner *corner;
- struct regulator *vdd_apc;
- struct clk *cpu_clk;
- struct regmap *tcsr;
- bool loop_disabled;
- u32 gcnt;
- unsigned long flags;
-
- struct fuse_corner *fuse_corners;
- struct corner *corners;
-
- const struct cpr_desc *desc;
- const struct acc_desc *acc_desc;
- const struct cpr_fuse *cpr_fuses;
-
- struct dentry *debugfs;
-};
-
-static bool cpr_is_allowed(struct cpr_drv *drv)
-{
- return !drv->loop_disabled;
-}
-
-static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
-{
- writel_relaxed(value, drv->base + offset);
-}
-
-static u32 cpr_read(struct cpr_drv *drv, u32 offset)
-{
- return readl_relaxed(drv->base + offset);
-}
-
-static void
-cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
-{
- u32 val;
-
- val = readl_relaxed(drv->base + offset);
- val &= ~mask;
- val |= value & mask;
- writel_relaxed(val, drv->base + offset);
-}
-
-static void cpr_irq_clr(struct cpr_drv *drv)
-{
- cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
-}
-
-static void cpr_irq_clr_nack(struct cpr_drv *drv)
-{
- cpr_irq_clr(drv);
- cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
-}
-
-static void cpr_irq_clr_ack(struct cpr_drv *drv)
-{
- cpr_irq_clr(drv);
- cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
-}
-
-static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
-{
- cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
-}
-
-static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
-{
- cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
-}
-
-static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
-{
- u32 val, mask;
- const struct cpr_desc *desc = drv->desc;
-
- /* Program Consecutive Up & Down */
- val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
- val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
- mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
- cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
- cpr_masked_write(drv, REG_RBCPR_CTL,
- RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
- RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
- corner->save_ctl);
- cpr_irq_set(drv, corner->save_irq);
-
- if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
- val = RBCPR_CTL_LOOP_EN;
- else
- val = 0;
- cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
-}
-
-static void cpr_ctl_disable(struct cpr_drv *drv)
-{
- cpr_irq_set(drv, 0);
- cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
- RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
- cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
- RBIF_TIMER_ADJ_CONS_UP_MASK |
- RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
- cpr_irq_clr(drv);
- cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
- cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
- cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
-}
-
-static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
-{
- u32 reg_val;
-
- reg_val = cpr_read(drv, REG_RBCPR_CTL);
- return reg_val & RBCPR_CTL_LOOP_EN;
-}
-
-static bool cpr_ctl_is_busy(struct cpr_drv *drv)
-{
- u32 reg_val;
-
- reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
- return reg_val & RBCPR_RESULT0_BUSY_MASK;
-}
-
-static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
-{
- corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
- corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
-}
-
-static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
-{
- u32 gcnt, ctl, irq, ro_sel, step_quot;
- struct fuse_corner *fuse = corner->fuse_corner;
- const struct cpr_desc *desc = drv->desc;
- int i;
-
- ro_sel = fuse->ring_osc_idx;
- gcnt = drv->gcnt;
- gcnt |= fuse->quot - corner->quot_adjust;
-
- /* Program the step quotient and idle clocks */
- step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
- step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
- cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
-
- /* Clear the target quotient value and gate count of all ROs */
- for (i = 0; i < CPR_NUM_RING_OSC; i++)
- cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
-
- cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
- ctl = corner->save_ctl;
- cpr_write(drv, REG_RBCPR_CTL, ctl);
- irq = corner->save_irq;
- cpr_irq_set(drv, irq);
- dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt,
- ctl, irq);
-}
-
-static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
- struct fuse_corner *end)
-{
- if (f == end)
- return;
-
- if (f < end) {
- for (f += 1; f <= end; f++)
- regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
- } else {
- for (f -= 1; f >= end; f--)
- regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
- }
-}
-
-static int cpr_pre_voltage(struct cpr_drv *drv,
- struct fuse_corner *fuse_corner,
- enum voltage_change_dir dir)
-{
- struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
-
- if (drv->tcsr && dir == DOWN)
- cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
-
- return 0;
-}
-
-static int cpr_post_voltage(struct cpr_drv *drv,
- struct fuse_corner *fuse_corner,
- enum voltage_change_dir dir)
-{
- struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
-
- if (drv->tcsr && dir == UP)
- cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
-
- return 0;
-}
-
-static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
- int new_uV, enum voltage_change_dir dir)
-{
- int ret;
- struct fuse_corner *fuse_corner = corner->fuse_corner;
-
- ret = cpr_pre_voltage(drv, fuse_corner, dir);
- if (ret)
- return ret;
-
- ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
- if (ret) {
- dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
- new_uV);
- return ret;
- }
-
- ret = cpr_post_voltage(drv, fuse_corner, dir);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv)
-{
- return drv->corner ? drv->corner - drv->corners + 1 : 0;
-}
-
-static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
-{
- u32 val, error_steps, reg_mask;
- int last_uV, new_uV, step_uV, ret;
- struct corner *corner;
- const struct cpr_desc *desc = drv->desc;
-
- if (dir != UP && dir != DOWN)
- return 0;
-
- step_uV = regulator_get_linear_step(drv->vdd_apc);
- if (!step_uV)
- return -EINVAL;
-
- corner = drv->corner;
-
- val = cpr_read(drv, REG_RBCPR_RESULT_0);
-
- error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
- error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
- last_uV = corner->last_uV;
-
- if (dir == UP) {
- if (desc->clamp_timer_interval &&
- error_steps < desc->up_threshold) {
- /*
- * Handle the case where another measurement started
- * after the interrupt was triggered due to a core
- * exiting from power collapse.
- */
- error_steps = max(desc->up_threshold,
- desc->vdd_apc_step_up_limit);
- }
-
- if (last_uV >= corner->max_uV) {
- cpr_irq_clr_nack(drv);
-
- /* Maximize the UP threshold */
- reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
- reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
- val = reg_mask;
- cpr_ctl_modify(drv, reg_mask, val);
-
- /* Disable UP interrupt */
- cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
-
- return 0;
- }
-
- if (error_steps > desc->vdd_apc_step_up_limit)
- error_steps = desc->vdd_apc_step_up_limit;
-
- /* Calculate new voltage */
- new_uV = last_uV + error_steps * step_uV;
- new_uV = min(new_uV, corner->max_uV);
-
- dev_dbg(drv->dev,
- "UP: -> new_uV: %d last_uV: %d perf state: %u\n",
- new_uV, last_uV, cpr_get_cur_perf_state(drv));
- } else {
- if (desc->clamp_timer_interval &&
- error_steps < desc->down_threshold) {
- /*
- * Handle the case where another measurement started
- * after the interrupt was triggered due to a core
- * exiting from power collapse.
- */
- error_steps = max(desc->down_threshold,
- desc->vdd_apc_step_down_limit);
- }
-
- if (last_uV <= corner->min_uV) {
- cpr_irq_clr_nack(drv);
-
- /* Enable auto nack down */
- reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
- val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
-
- cpr_ctl_modify(drv, reg_mask, val);
-
- /* Disable DOWN interrupt */
- cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
-
- return 0;
- }
-
- if (error_steps > desc->vdd_apc_step_down_limit)
- error_steps = desc->vdd_apc_step_down_limit;
-
- /* Calculate new voltage */
- new_uV = last_uV - error_steps * step_uV;
- new_uV = max(new_uV, corner->min_uV);
-
- dev_dbg(drv->dev,
- "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n",
- new_uV, last_uV, cpr_get_cur_perf_state(drv));
- }
-
- ret = cpr_scale_voltage(drv, corner, new_uV, dir);
- if (ret) {
- cpr_irq_clr_nack(drv);
- return ret;
- }
- drv->corner->last_uV = new_uV;
-
- if (dir == UP) {
- /* Disable auto nack down */
- reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
- val = 0;
- } else {
- /* Restore default threshold for UP */
- reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
- reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
- val = desc->up_threshold;
- val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
- }
-
- cpr_ctl_modify(drv, reg_mask, val);
-
- /* Re-enable default interrupts */
- cpr_irq_set(drv, CPR_INT_DEFAULT);
-
- /* Ack */
- cpr_irq_clr_ack(drv);
-
- return 0;
-}
-
-static irqreturn_t cpr_irq_handler(int irq, void *dev)
-{
- struct cpr_drv *drv = dev;
- const struct cpr_desc *desc = drv->desc;
- irqreturn_t ret = IRQ_HANDLED;
- u32 val;
-
- mutex_lock(&drv->lock);
-
- val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
- if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
- val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
-
- dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
-
- if (!cpr_ctl_is_enabled(drv)) {
- dev_dbg(drv->dev, "CPR is disabled\n");
- ret = IRQ_NONE;
- } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) {
- dev_dbg(drv->dev, "CPR measurement is not ready\n");
- } else if (!cpr_is_allowed(drv)) {
- val = cpr_read(drv, REG_RBCPR_CTL);
- dev_err_ratelimited(drv->dev,
- "Interrupt broken? RBCPR_CTL = %#02x\n",
- val);
- ret = IRQ_NONE;
- } else {
- /*
- * Following sequence of handling is as per each IRQ's
- * priority
- */
- if (val & CPR_INT_UP) {
- cpr_scale(drv, UP);
- } else if (val & CPR_INT_DOWN) {
- cpr_scale(drv, DOWN);
- } else if (val & CPR_INT_MIN) {
- cpr_irq_clr_nack(drv);
- } else if (val & CPR_INT_MAX) {
- cpr_irq_clr_nack(drv);
- } else if (val & CPR_INT_MID) {
- /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
- dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
- } else {
- dev_dbg(drv->dev,
- "IRQ occurred for unknown flag (%#08x)\n", val);
- }
-
- /* Save register values for the corner */
- cpr_corner_save(drv, drv->corner);
- }
-
- mutex_unlock(&drv->lock);
-
- return ret;
-}
-
-static int cpr_enable(struct cpr_drv *drv)
-{
- int ret;
-
- ret = regulator_enable(drv->vdd_apc);
- if (ret)
- return ret;
-
- mutex_lock(&drv->lock);
-
- if (cpr_is_allowed(drv) && drv->corner) {
- cpr_irq_clr(drv);
- cpr_corner_restore(drv, drv->corner);
- cpr_ctl_enable(drv, drv->corner);
- }
-
- mutex_unlock(&drv->lock);
-
- return 0;
-}
-
-static int cpr_disable(struct cpr_drv *drv)
-{
- mutex_lock(&drv->lock);
-
- if (cpr_is_allowed(drv)) {
- cpr_ctl_disable(drv);
- cpr_irq_clr(drv);
- }
-
- mutex_unlock(&drv->lock);
-
- return regulator_disable(drv->vdd_apc);
-}
-
-static int cpr_config(struct cpr_drv *drv)
-{
- int i;
- u32 val, gcnt;
- struct corner *corner;
- const struct cpr_desc *desc = drv->desc;
-
- /* Disable interrupt and CPR */
- cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
- cpr_write(drv, REG_RBCPR_CTL, 0);
-
- /* Program the default HW ceiling, floor and vlevel */
- val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
- << RBIF_LIMIT_CEILING_SHIFT;
- val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
- cpr_write(drv, REG_RBIF_LIMIT, val);
- cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
-
- /*
- * Clear the target quotient value and gate count of all
- * ring oscillators
- */
- for (i = 0; i < CPR_NUM_RING_OSC; i++)
- cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
-
- /* Init and save gcnt */
- gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000;
- gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
- gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
- drv->gcnt = gcnt;
-
- /* Program the delay count for the timer */
- val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
- cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
- dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
- desc->timer_delay_us);
-
- /* Program Consecutive Up & Down */
- val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
- val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
- val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
- cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
-
- /* Program the control register */
- val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
- val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
- val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
- val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
- cpr_write(drv, REG_RBCPR_CTL, val);
-
- for (i = 0; i < drv->num_corners; i++) {
- corner = &drv->corners[i];
- corner->save_ctl = val;
- corner->save_irq = CPR_INT_DEFAULT;
- }
-
- cpr_irq_set(drv, CPR_INT_DEFAULT);
-
- val = cpr_read(drv, REG_RBCPR_VERSION);
- if (val <= RBCPR_VER_2)
- drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
-
- return 0;
-}
-
-static int cpr_set_performance_state(struct generic_pm_domain *domain,
- unsigned int state)
-{
- struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
- struct corner *corner, *end;
- enum voltage_change_dir dir;
- int ret = 0, new_uV;
-
- mutex_lock(&drv->lock);
-
- dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n",
- __func__, state, cpr_get_cur_perf_state(drv));
-
- /*
- * Determine new corner we're going to.
- * Remove one since lowest performance state is 1.
- */
- corner = drv->corners + state - 1;
- end = &drv->corners[drv->num_corners - 1];
- if (corner > end || corner < drv->corners) {
- ret = -EINVAL;
- goto unlock;
- }
-
- /* Determine direction */
- if (drv->corner > corner)
- dir = DOWN;
- else if (drv->corner < corner)
- dir = UP;
- else
- dir = NO_CHANGE;
-
- if (cpr_is_allowed(drv))
- new_uV = corner->last_uV;
- else
- new_uV = corner->uV;
-
- if (cpr_is_allowed(drv))
- cpr_ctl_disable(drv);
-
- ret = cpr_scale_voltage(drv, corner, new_uV, dir);
- if (ret)
- goto unlock;
-
- if (cpr_is_allowed(drv)) {
- cpr_irq_clr(drv);
- if (drv->corner != corner)
- cpr_corner_restore(drv, corner);
- cpr_ctl_enable(drv, corner);
- }
-
- drv->corner = corner;
-
-unlock:
- mutex_unlock(&drv->lock);
-
- return ret;
-}
-
-static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
-{
- struct nvmem_cell *cell;
- ssize_t len;
- char *ret;
- int i;
-
- *data = 0;
-
- cell = nvmem_cell_get(dev, cname);
- if (IS_ERR(cell)) {
- if (PTR_ERR(cell) != -EPROBE_DEFER)
- dev_err(dev, "undefined cell %s\n", cname);
- return PTR_ERR(cell);
- }
-
- ret = nvmem_cell_read(cell, &len);
- nvmem_cell_put(cell);
- if (IS_ERR(ret)) {
- dev_err(dev, "can't read cell %s\n", cname);
- return PTR_ERR(ret);
- }
-
- for (i = 0; i < len; i++)
- *data |= ret[i] << (8 * i);
-
- kfree(ret);
- dev_dbg(dev, "efuse read(%s) = %x, bytes %zd\n", cname, *data, len);
-
- return 0;
-}
-
-static int
-cpr_populate_ring_osc_idx(struct cpr_drv *drv)
-{
- struct fuse_corner *fuse = drv->fuse_corners;
- struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
- const struct cpr_fuse *fuses = drv->cpr_fuses;
- u32 data;
- int ret;
-
- for (; fuse < end; fuse++, fuses++) {
- ret = cpr_read_efuse(drv->dev, fuses->ring_osc,
- &data);
- if (ret)
- return ret;
- fuse->ring_osc_idx = data;
- }
-
- return 0;
-}
-
-static int cpr_read_fuse_uV(const struct cpr_desc *desc,
- const struct fuse_corner_data *fdata,
- const char *init_v_efuse,
- int step_volt,
- struct cpr_drv *drv)
-{
- int step_size_uV, steps, uV;
- u32 bits = 0;
- int ret;
-
- ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits);
- if (ret)
- return ret;
-
- steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
- /* Not two's complement.. instead highest bit is sign bit */
- if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
- steps = -steps;
-
- step_size_uV = desc->cpr_fuses.init_voltage_step;
-
- uV = fdata->ref_uV + steps * step_size_uV;
- return DIV_ROUND_UP(uV, step_volt) * step_volt;
-}
-
-static int cpr_fuse_corner_init(struct cpr_drv *drv)
-{
- const struct cpr_desc *desc = drv->desc;
- const struct cpr_fuse *fuses = drv->cpr_fuses;
- const struct acc_desc *acc_desc = drv->acc_desc;
- int i;
- unsigned int step_volt;
- struct fuse_corner_data *fdata;
- struct fuse_corner *fuse, *end;
- int uV;
- const struct reg_sequence *accs;
- int ret;
-
- accs = acc_desc->settings;
-
- step_volt = regulator_get_linear_step(drv->vdd_apc);
- if (!step_volt)
- return -EINVAL;
-
- /* Populate fuse_corner members */
- fuse = drv->fuse_corners;
- end = &fuse[desc->num_fuse_corners - 1];
- fdata = desc->cpr_fuses.fuse_corner_data;
-
- for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
- /*
- * Update SoC voltages: platforms might choose a different
- * regulators than the one used to characterize the algorithms
- * (ie, init_voltage_step).
- */
- fdata->min_uV = roundup(fdata->min_uV, step_volt);
- fdata->max_uV = roundup(fdata->max_uV, step_volt);
-
- /* Populate uV */
- uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
- step_volt, drv);
- if (uV < 0)
- return uV;
-
- fuse->min_uV = fdata->min_uV;
- fuse->max_uV = fdata->max_uV;
- fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
-
- if (fuse == end) {
- /*
- * Allow the highest fuse corner's PVS voltage to
- * define the ceiling voltage for that corner in order
- * to support SoC's in which variable ceiling values
- * are required.
- */
- end->max_uV = max(end->max_uV, end->uV);
- }
-
- /* Populate target quotient by scaling */
- ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot);
- if (ret)
- return ret;
-
- fuse->quot *= fdata->quot_scale;
- fuse->quot += fdata->quot_offset;
- fuse->quot += fdata->quot_adjust;
- fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
-
- /* Populate acc settings */
- fuse->accs = accs;
- fuse->num_accs = acc_desc->num_regs_per_fuse;
- accs += acc_desc->num_regs_per_fuse;
- }
-
- /*
- * Restrict all fuse corner PVS voltages based upon per corner
- * ceiling and floor voltages.
- */
- for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
- if (fuse->uV > fuse->max_uV)
- fuse->uV = fuse->max_uV;
- else if (fuse->uV < fuse->min_uV)
- fuse->uV = fuse->min_uV;
-
- ret = regulator_is_supported_voltage(drv->vdd_apc,
- fuse->min_uV,
- fuse->min_uV);
- if (!ret) {
- dev_err(drv->dev,
- "min uV: %d (fuse corner: %d) not supported by regulator\n",
- fuse->min_uV, i);
- return -EINVAL;
- }
-
- ret = regulator_is_supported_voltage(drv->vdd_apc,
- fuse->max_uV,
- fuse->max_uV);
- if (!ret) {
- dev_err(drv->dev,
- "max uV: %d (fuse corner: %d) not supported by regulator\n",
- fuse->max_uV, i);
- return -EINVAL;
- }
-
- dev_dbg(drv->dev,
- "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n",
- i, fuse->min_uV, fuse->uV, fuse->max_uV,
- fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
- }
-
- return 0;
-}
-
-static int cpr_calculate_scaling(const char *quot_offset,
- struct cpr_drv *drv,
- const struct fuse_corner_data *fdata,
- const struct corner *corner)
-{
- u32 quot_diff = 0;
- unsigned long freq_diff;
- int scaling;
- const struct fuse_corner *fuse, *prev_fuse;
- int ret;
-
- fuse = corner->fuse_corner;
- prev_fuse = fuse - 1;
-
- if (quot_offset) {
- ret = cpr_read_efuse(drv->dev, quot_offset, "_diff);
- if (ret)
- return ret;
-
- quot_diff *= fdata->quot_offset_scale;
- quot_diff += fdata->quot_offset_adjust;
- } else {
- quot_diff = fuse->quot - prev_fuse->quot;
- }
-
- freq_diff = fuse->max_freq - prev_fuse->max_freq;
- freq_diff /= 1000000; /* Convert to MHz */
- scaling = 1000 * quot_diff / freq_diff;
- return min(scaling, fdata->max_quot_scale);
-}
-
-static int cpr_interpolate(const struct corner *corner, int step_volt,
- const struct fuse_corner_data *fdata)
-{
- unsigned long f_high, f_low, f_diff;
- int uV_high, uV_low, uV;
- u64 temp, temp_limit;
- const struct fuse_corner *fuse, *prev_fuse;
-
- fuse = corner->fuse_corner;
- prev_fuse = fuse - 1;
-
- f_high = fuse->max_freq;
- f_low = prev_fuse->max_freq;
- uV_high = fuse->uV;
- uV_low = prev_fuse->uV;
- f_diff = fuse->max_freq - corner->freq;
-
- /*
- * Don't interpolate in the wrong direction. This could happen
- * if the adjusted fuse voltage overlaps with the previous fuse's
- * adjusted voltage.
- */
- if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
- return corner->uV;
-
- temp = f_diff * (uV_high - uV_low);
- do_div(temp, f_high - f_low);
-
- /*
- * max_volt_scale has units of uV/MHz while freq values
- * have units of Hz. Divide by 1000000 to convert to.
- */
- temp_limit = f_diff * fdata->max_volt_scale;
- do_div(temp_limit, 1000000);
-
- uV = uV_high - min(temp, temp_limit);
- return roundup(uV, step_volt);
-}
-
-static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
-{
- struct device_node *np;
- unsigned int fuse_corner = 0;
-
- np = dev_pm_opp_get_of_node(opp);
- if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner))
- pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
- __func__);
-
- of_node_put(np);
-
- return fuse_corner;
-}
-
-static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref,
- struct device *cpu_dev)
-{
- u64 rate = 0;
- struct device_node *ref_np;
- struct device_node *desc_np;
- struct device_node *child_np = NULL;
- struct device_node *child_req_np = NULL;
-
- desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
- if (!desc_np)
- return 0;
-
- ref_np = dev_pm_opp_get_of_node(ref);
- if (!ref_np)
- goto out_ref;
-
- do {
- of_node_put(child_req_np);
- child_np = of_get_next_available_child(desc_np, child_np);
- child_req_np = of_parse_phandle(child_np, "required-opps", 0);
- } while (child_np && child_req_np != ref_np);
-
- if (child_np && child_req_np == ref_np)
- of_property_read_u64(child_np, "opp-hz", &rate);
-
- of_node_put(child_req_np);
- of_node_put(child_np);
- of_node_put(ref_np);
-out_ref:
- of_node_put(desc_np);
-
- return (unsigned long) rate;
-}
-
-static int cpr_corner_init(struct cpr_drv *drv)
-{
- const struct cpr_desc *desc = drv->desc;
- const struct cpr_fuse *fuses = drv->cpr_fuses;
- int i, level, scaling = 0;
- unsigned int fnum, fc;
- const char *quot_offset;
- struct fuse_corner *fuse, *prev_fuse;
- struct corner *corner, *end;
- struct corner_data *cdata;
- const struct fuse_corner_data *fdata;
- bool apply_scaling;
- unsigned long freq_diff, freq_diff_mhz;
- unsigned long freq;
- int step_volt = regulator_get_linear_step(drv->vdd_apc);
- struct dev_pm_opp *opp;
-
- if (!step_volt)
- return -EINVAL;
-
- corner = drv->corners;
- end = &corner[drv->num_corners - 1];
-
- cdata = devm_kcalloc(drv->dev, drv->num_corners,
- sizeof(struct corner_data),
- GFP_KERNEL);
- if (!cdata)
- return -ENOMEM;
-
- /*
- * Store maximum frequency for each fuse corner based on the frequency
- * plan
- */
- for (level = 1; level <= drv->num_corners; level++) {
- opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level);
- if (IS_ERR(opp))
- return -EINVAL;
- fc = cpr_get_fuse_corner(opp);
- if (!fc) {
- dev_pm_opp_put(opp);
- return -EINVAL;
- }
- fnum = fc - 1;
- freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev);
- if (!freq) {
- dev_pm_opp_put(opp);
- return -EINVAL;
- }
- cdata[level - 1].fuse_corner = fnum;
- cdata[level - 1].freq = freq;
-
- fuse = &drv->fuse_corners[fnum];
- dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
- freq, dev_pm_opp_get_level(opp) - 1, fnum);
- if (freq > fuse->max_freq)
- fuse->max_freq = freq;
- dev_pm_opp_put(opp);
- }
-
- /*
- * Get the quotient adjustment scaling factor, according to:
- *
- * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
- * / (freq(corner_N) - freq(corner_N-1)), max_factor)
- *
- * QUOT(corner_N): quotient read from fuse for fuse corner N
- * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1)
- * freq(corner_N): max frequency in MHz supported by fuse corner N
- * freq(corner_N-1): max frequency in MHz supported by fuse corner
- * (N - 1)
- *
- * Then walk through the corners mapped to each fuse corner
- * and calculate the quotient adjustment for each one using the
- * following formula:
- *
- * quot_adjust = (freq_max - freq_corner) * scaling / 1000
- *
- * freq_max: max frequency in MHz supported by the fuse corner
- * freq_corner: frequency in MHz corresponding to the corner
- * scaling: calculated from above equation
- *
- *
- * + +
- * | v |
- * q | f c o | f c
- * u | c l | c
- * o | f t | f
- * t | c a | c
- * | c f g | c f
- * | e |
- * +--------------- +----------------
- * 0 1 2 3 4 5 6 0 1 2 3 4 5 6
- * corner corner
- *
- * c = corner
- * f = fuse corner
- *
- */
- for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
- fnum = cdata[i].fuse_corner;
- fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
- quot_offset = fuses[fnum].quotient_offset;
- fuse = &drv->fuse_corners[fnum];
- if (fnum)
- prev_fuse = &drv->fuse_corners[fnum - 1];
- else
- prev_fuse = NULL;
-
- corner->fuse_corner = fuse;
- corner->freq = cdata[i].freq;
- corner->uV = fuse->uV;
-
- if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
- scaling = cpr_calculate_scaling(quot_offset, drv,
- fdata, corner);
- if (scaling < 0)
- return scaling;
-
- apply_scaling = true;
- } else if (corner->freq == fuse->max_freq) {
- /* This is a fuse corner; don't scale anything */
- apply_scaling = false;
- }
-
- if (apply_scaling) {
- freq_diff = fuse->max_freq - corner->freq;
- freq_diff_mhz = freq_diff / 1000000;
- corner->quot_adjust = scaling * freq_diff_mhz / 1000;
-
- corner->uV = cpr_interpolate(corner, step_volt, fdata);
- }
-
- corner->max_uV = fuse->max_uV;
- corner->min_uV = fuse->min_uV;
- corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
- corner->last_uV = corner->uV;
-
- /* Reduce the ceiling voltage if needed */
- if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
- corner->max_uV = corner->uV;
- else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
- corner->max_uV = max(corner->min_uV, fuse->uV);
-
- dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
- corner->min_uV, corner->uV, corner->max_uV,
- fuse->quot - corner->quot_adjust);
- }
-
- return 0;
-}
-
-static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
-{
- const struct cpr_desc *desc = drv->desc;
- struct cpr_fuse *fuses;
- int i;
-
- fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners,
- sizeof(struct cpr_fuse),
- GFP_KERNEL);
- if (!fuses)
- return ERR_PTR(-ENOMEM);
-
- for (i = 0; i < desc->num_fuse_corners; i++) {
- char tbuf[32];
-
- snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
- fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
- if (!fuses[i].ring_osc)
- return ERR_PTR(-ENOMEM);
-
- snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
- fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
- GFP_KERNEL);
- if (!fuses[i].init_voltage)
- return ERR_PTR(-ENOMEM);
-
- snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
- fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
- if (!fuses[i].quotient)
- return ERR_PTR(-ENOMEM);
-
- snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
- fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
- GFP_KERNEL);
- if (!fuses[i].quotient_offset)
- return ERR_PTR(-ENOMEM);
- }
-
- return fuses;
-}
-
-static void cpr_set_loop_allowed(struct cpr_drv *drv)
-{
- drv->loop_disabled = false;
-}
-
-static int cpr_init_parameters(struct cpr_drv *drv)
-{
- const struct cpr_desc *desc = drv->desc;
- struct clk *clk;
-
- clk = clk_get(drv->dev, "ref");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- drv->ref_clk_khz = clk_get_rate(clk) / 1000;
- clk_put(clk);
-
- if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK ||
- desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK ||
- desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK ||
- desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK ||
- desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK ||
- desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK)
- return -EINVAL;
-
- dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
- desc->up_threshold, desc->down_threshold);
-
- return 0;
-}
-
-static int cpr_find_initial_corner(struct cpr_drv *drv)
-{
- unsigned long rate;
- const struct corner *end;
- struct corner *iter;
- unsigned int i = 0;
-
- if (!drv->cpu_clk) {
- dev_err(drv->dev, "cannot get rate from NULL clk\n");
- return -EINVAL;
- }
-
- end = &drv->corners[drv->num_corners - 1];
- rate = clk_get_rate(drv->cpu_clk);
-
- /*
- * Some bootloaders set a CPU clock frequency that is not defined
- * in the OPP table. When running at an unlisted frequency,
- * cpufreq_online() will change to the OPP which has the lowest
- * frequency, at or above the unlisted frequency.
- * Since cpufreq_online() always "rounds up" in the case of an
- * unlisted frequency, this function always "rounds down" in case
- * of an unlisted frequency. That way, when cpufreq_online()
- * triggers the first ever call to cpr_set_performance_state(),
- * it will correctly determine the direction as UP.
- */
- for (iter = drv->corners; iter <= end; iter++) {
- if (iter->freq > rate)
- break;
- i++;
- if (iter->freq == rate) {
- drv->corner = iter;
- break;
- }
- if (iter->freq < rate)
- drv->corner = iter;
- }
-
- if (!drv->corner) {
- dev_err(drv->dev, "boot up corner not found\n");
- return -EINVAL;
- }
-
- dev_dbg(drv->dev, "boot up perf state: %u\n", i);
-
- return 0;
-}
-
-static const struct cpr_desc qcs404_cpr_desc = {
- .num_fuse_corners = 3,
- .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
- .step_quot = (int []){ 25, 25, 25, },
- .timer_delay_us = 5000,
- .timer_cons_up = 0,
- .timer_cons_down = 2,
- .up_threshold = 1,
- .down_threshold = 3,
- .idle_clocks = 15,
- .gcnt_us = 1,
- .vdd_apc_step_up_limit = 1,
- .vdd_apc_step_down_limit = 1,
- .cpr_fuses = {
- .init_voltage_step = 8000,
- .init_voltage_width = 6,
- .fuse_corner_data = (struct fuse_corner_data[]){
- /* fuse corner 0 */
- {
- .ref_uV = 1224000,
- .max_uV = 1224000,
- .min_uV = 1048000,
- .max_volt_scale = 0,
- .max_quot_scale = 0,
- .quot_offset = 0,
- .quot_scale = 1,
- .quot_adjust = 0,
- .quot_offset_scale = 5,
- .quot_offset_adjust = 0,
- },
- /* fuse corner 1 */
- {
- .ref_uV = 1288000,
- .max_uV = 1288000,
- .min_uV = 1048000,
- .max_volt_scale = 2000,
- .max_quot_scale = 1400,
- .quot_offset = 0,
- .quot_scale = 1,
- .quot_adjust = -20,
- .quot_offset_scale = 5,
- .quot_offset_adjust = 0,
- },
- /* fuse corner 2 */
- {
- .ref_uV = 1352000,
- .max_uV = 1384000,
- .min_uV = 1088000,
- .max_volt_scale = 2000,
- .max_quot_scale = 1400,
- .quot_offset = 0,
- .quot_scale = 1,
- .quot_adjust = 0,
- .quot_offset_scale = 5,
- .quot_offset_adjust = 0,
- },
- },
- },
-};
-
-static const struct acc_desc qcs404_acc_desc = {
- .settings = (struct reg_sequence[]){
- { 0xb120, 0x1041040 },
- { 0xb124, 0x41 },
- { 0xb120, 0x0 },
- { 0xb124, 0x0 },
- { 0xb120, 0x0 },
- { 0xb124, 0x0 },
- },
- .config = (struct reg_sequence[]){
- { 0xb138, 0xff },
- { 0xb130, 0x5555 },
- },
- .num_regs_per_fuse = 2,
-};
-
-static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
- .cpr_desc = &qcs404_cpr_desc,
- .acc_desc = &qcs404_acc_desc,
-};
-
-static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd,
- struct dev_pm_opp *opp)
-{
- return dev_pm_opp_get_level(opp);
-}
-
-static int cpr_power_off(struct generic_pm_domain *domain)
-{
- struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
-
- return cpr_disable(drv);
-}
-
-static int cpr_power_on(struct generic_pm_domain *domain)
-{
- struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
-
- return cpr_enable(drv);
-}
-
-static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
- const struct acc_desc *acc_desc = drv->acc_desc;
- int ret = 0;
-
- mutex_lock(&drv->lock);
-
- dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
-
- /*
- * This driver only supports scaling voltage for a CPU cluster
- * where all CPUs in the cluster share a single regulator.
- * Therefore, save the struct device pointer only for the first
- * CPU device that gets attached. There is no need to do any
- * additional initialization when further CPUs get attached.
- */
- if (drv->attached_cpu_dev)
- goto unlock;
-
- /*
- * cpr_scale_voltage() requires the direction (if we are changing
- * to a higher or lower OPP). The first time
- * cpr_set_performance_state() is called, there is no previous
- * performance state defined. Therefore, we call
- * cpr_find_initial_corner() that gets the CPU clock frequency
- * set by the bootloader, so that we can determine the direction
- * the first time cpr_set_performance_state() is called.
- */
- drv->cpu_clk = devm_clk_get(dev, NULL);
- if (IS_ERR(drv->cpu_clk)) {
- ret = PTR_ERR(drv->cpu_clk);
- if (ret != -EPROBE_DEFER)
- dev_err(drv->dev, "could not get cpu clk: %d\n", ret);
- goto unlock;
- }
- drv->attached_cpu_dev = dev;
-
- dev_dbg(drv->dev, "using cpu clk from: %s\n",
- dev_name(drv->attached_cpu_dev));
-
- /*
- * Everything related to (virtual) corners has to be initialized
- * here, when attaching to the power domain, since we need to know
- * the maximum frequency for each fuse corner, and this is only
- * available after the cpufreq driver has attached to us.
- * The reason for this is that we need to know the highest
- * frequency associated with each fuse corner.
- */
- ret = dev_pm_opp_get_opp_count(&drv->pd.dev);
- if (ret < 0) {
- dev_err(drv->dev, "could not get OPP count\n");
- goto unlock;
- }
- drv->num_corners = ret;
-
- if (drv->num_corners < 2) {
- dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
- ret = -EINVAL;
- goto unlock;
- }
-
- drv->corners = devm_kcalloc(drv->dev, drv->num_corners,
- sizeof(*drv->corners),
- GFP_KERNEL);
- if (!drv->corners) {
- ret = -ENOMEM;
- goto unlock;
- }
-
- ret = cpr_corner_init(drv);
- if (ret)
- goto unlock;
-
- cpr_set_loop_allowed(drv);
-
- ret = cpr_init_parameters(drv);
- if (ret)
- goto unlock;
-
- /* Configure CPR HW but keep it disabled */
- ret = cpr_config(drv);
- if (ret)
- goto unlock;
-
- ret = cpr_find_initial_corner(drv);
- if (ret)
- goto unlock;
-
- if (acc_desc->config)
- regmap_multi_reg_write(drv->tcsr, acc_desc->config,
- acc_desc->num_regs_per_fuse);
-
- /* Enable ACC if required */
- if (acc_desc->enable_mask)
- regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
- acc_desc->enable_mask,
- acc_desc->enable_mask);
-
- dev_info(drv->dev, "driver initialized with %u OPPs\n",
- drv->num_corners);
-
-unlock:
- mutex_unlock(&drv->lock);
-
- return ret;
-}
-
-static int cpr_debug_info_show(struct seq_file *s, void *unused)
-{
- u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
- u32 step_dn, step_up, error, error_lt0, busy;
- struct cpr_drv *drv = s->private;
- struct fuse_corner *fuse_corner;
- struct corner *corner;
-
- corner = drv->corner;
- fuse_corner = corner->fuse_corner;
-
- seq_printf(s, "corner, current_volt = %d uV\n",
- corner->last_uV);
-
- ro_sel = fuse_corner->ring_osc_idx;
- gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
- seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt);
-
- ctl = cpr_read(drv, REG_RBCPR_CTL);
- seq_printf(s, "rbcpr_ctl = %#02X\n", ctl);
-
- irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
- seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status);
-
- reg = cpr_read(drv, REG_RBCPR_RESULT_0);
- seq_printf(s, "rbcpr_result_0 = %#02X\n", reg);
-
- step_dn = reg & 0x01;
- step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
- seq_printf(s, " [step_dn = %u", step_dn);
-
- seq_printf(s, ", step_up = %u", step_up);
-
- error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
- & RBCPR_RESULT0_ERROR_STEPS_MASK;
- seq_printf(s, ", error_steps = %u", error_steps);
-
- error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
- seq_printf(s, ", error = %u", error);
-
- error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
- seq_printf(s, ", error_lt_0 = %u", error_lt0);
-
- busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
- seq_printf(s, ", busy = %u]\n", busy);
-
- return 0;
-}
-DEFINE_SHOW_ATTRIBUTE(cpr_debug_info);
-
-static void cpr_debugfs_init(struct cpr_drv *drv)
-{
- drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
-
- debugfs_create_file("debug_info", 0444, drv->debugfs,
- drv, &cpr_debug_info_fops);
-}
-
-static int cpr_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct device *dev = &pdev->dev;
- struct cpr_drv *drv;
- int irq, ret;
- const struct cpr_acc_desc *data;
- struct device_node *np;
- u32 cpr_rev = FUSE_REVISION_UNKNOWN;
-
- data = of_device_get_match_data(dev);
- if (!data || !data->cpr_desc || !data->acc_desc)
- return -EINVAL;
-
- drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
- if (!drv)
- return -ENOMEM;
- drv->dev = dev;
- drv->desc = data->cpr_desc;
- drv->acc_desc = data->acc_desc;
-
- drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
- sizeof(*drv->fuse_corners),
- GFP_KERNEL);
- if (!drv->fuse_corners)
- return -ENOMEM;
-
- np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
- if (!np)
- return -ENODEV;
-
- drv->tcsr = syscon_node_to_regmap(np);
- of_node_put(np);
- if (IS_ERR(drv->tcsr))
- return PTR_ERR(drv->tcsr);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- drv->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(drv->base))
- return PTR_ERR(drv->base);
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return -EINVAL;
-
- drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
- if (IS_ERR(drv->vdd_apc))
- return PTR_ERR(drv->vdd_apc);
-
- /*
- * Initialize fuse corners, since it simply depends
- * on data in efuses.
- * Everything related to (virtual) corners has to be
- * initialized after attaching to the power domain,
- * since it depends on the CPU's OPP table.
- */
- ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
- if (ret)
- return ret;
-
- drv->cpr_fuses = cpr_get_fuses(drv);
- if (IS_ERR(drv->cpr_fuses))
- return PTR_ERR(drv->cpr_fuses);
-
- ret = cpr_populate_ring_osc_idx(drv);
- if (ret)
- return ret;
-
- ret = cpr_fuse_corner_init(drv);
- if (ret)
- return ret;
-
- mutex_init(&drv->lock);
-
- ret = devm_request_threaded_irq(dev, irq, NULL,
- cpr_irq_handler,
- IRQF_ONESHOT | IRQF_TRIGGER_RISING,
- "cpr", drv);
- if (ret)
- return ret;
-
- drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
- GFP_KERNEL);
- if (!drv->pd.name)
- return -EINVAL;
-
- drv->pd.power_off = cpr_power_off;
- drv->pd.power_on = cpr_power_on;
- drv->pd.set_performance_state = cpr_set_performance_state;
- drv->pd.opp_to_performance_state = cpr_get_performance_state;
- drv->pd.attach_dev = cpr_pd_attach_dev;
-
- ret = pm_genpd_init(&drv->pd, NULL, true);
- if (ret)
- return ret;
-
- ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
- if (ret)
- return ret;
-
- platform_set_drvdata(pdev, drv);
- cpr_debugfs_init(drv);
-
- return 0;
-}
-
-static int cpr_remove(struct platform_device *pdev)
-{
- struct cpr_drv *drv = platform_get_drvdata(pdev);
-
- if (cpr_is_allowed(drv)) {
- cpr_ctl_disable(drv);
- cpr_irq_set(drv, 0);
- }
-
- of_genpd_del_provider(pdev->dev.of_node);
- pm_genpd_remove(&drv->pd);
-
- debugfs_remove_recursive(drv->debugfs);
-
- return 0;
-}
-
-static const struct of_device_id cpr_match_table[] = {
- { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
- { }
-};
-MODULE_DEVICE_TABLE(of, cpr_match_table);
-
-static struct platform_driver cpr_driver = {
- .probe = cpr_probe,
- .remove = cpr_remove,
- .driver = {
- .name = "qcom-cpr",
- .of_match_table = cpr_match_table,
- },
-};
-module_platform_driver(cpr_driver);
-
-MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Rockchip IO Voltage Domain driver
- *
- * Copyright 2014 MundoReader S.L.
- * Copyright 2014 Google, Inc.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/regulator/consumer.h>
-
-#define MAX_SUPPLIES 16
-
-/*
- * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
- * "Recommended Operating Conditions" for "Digital GPIO". When the typical
- * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
- *
- * They are used like this:
- * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
- * SoC we're at 3.3.
- * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
- * that to be an error.
- */
-#define MAX_VOLTAGE_1_8 1980000
-#define MAX_VOLTAGE_3_3 3600000
-
-#define PX30_IO_VSEL 0x180
-#define PX30_IO_VSEL_VCCIO6_SRC BIT(0)
-#define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
-
-#define RK3288_SOC_CON2 0x24c
-#define RK3288_SOC_CON2_FLASH0 BIT(7)
-#define RK3288_SOC_FLASH_SUPPLY_NUM 2
-
-#define RK3328_SOC_CON4 0x410
-#define RK3328_SOC_CON4_VCCIO2 BIT(7)
-#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
-
-#define RK3368_SOC_CON15 0x43c
-#define RK3368_SOC_CON15_FLASH0 BIT(14)
-#define RK3368_SOC_FLASH_SUPPLY_NUM 2
-
-#define RK3399_PMUGRF_CON0 0x180
-#define RK3399_PMUGRF_CON0_VSEL BIT(8)
-#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
-
-struct rockchip_iodomain;
-
-/**
- * @supplies: voltage settings matching the register bits.
- */
-struct rockchip_iodomain_soc_data {
- int grf_offset;
- const char *supply_names[MAX_SUPPLIES];
- void (*init)(struct rockchip_iodomain *iod);
-};
-
-struct rockchip_iodomain_supply {
- struct rockchip_iodomain *iod;
- struct regulator *reg;
- struct notifier_block nb;
- int idx;
-};
-
-struct rockchip_iodomain {
- struct device *dev;
- struct regmap *grf;
- const struct rockchip_iodomain_soc_data *soc_data;
- struct rockchip_iodomain_supply supplies[MAX_SUPPLIES];
-};
-
-static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply,
- int uV)
-{
- struct rockchip_iodomain *iod = supply->iod;
- u32 val;
- int ret;
-
- /* set value bit */
- val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1;
- val <<= supply->idx;
-
- /* apply hiword-mask */
- val |= (BIT(supply->idx) << 16);
-
- ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val);
- if (ret)
- dev_err(iod->dev, "Couldn't write to GRF\n");
-
- return ret;
-}
-
-static int rockchip_iodomain_notify(struct notifier_block *nb,
- unsigned long event,
- void *data)
-{
- struct rockchip_iodomain_supply *supply =
- container_of(nb, struct rockchip_iodomain_supply, nb);
- int uV;
- int ret;
-
- /*
- * According to Rockchip it's important to keep the SoC IO domain
- * higher than (or equal to) the external voltage. That means we need
- * to change it before external voltage changes happen in the case
- * of an increase.
- *
- * Note that in the "pre" change we pick the max possible voltage that
- * the regulator might end up at (the client requests a range and we
- * don't know for certain the exact voltage). Right now we rely on the
- * slop in MAX_VOLTAGE_1_8 and MAX_VOLTAGE_3_3 to save us if clients
- * request something like a max of 3.6V when they really want 3.3V.
- * We could attempt to come up with better rules if this fails.
- */
- if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
- struct pre_voltage_change_data *pvc_data = data;
-
- uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
- } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
- REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
- uV = (unsigned long)data;
- } else {
- return NOTIFY_OK;
- }
-
- dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
-
- if (uV > MAX_VOLTAGE_3_3) {
- dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
-
- if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
- return NOTIFY_BAD;
- }
-
- ret = rockchip_iodomain_write(supply, uV);
- if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
- return NOTIFY_BAD;
-
- dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
- return NOTIFY_OK;
-}
-
-static void px30_iodomain_init(struct rockchip_iodomain *iod)
-{
- int ret;
- u32 val;
-
- /* if no VCCIO6 supply we should leave things alone */
- if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg)
- return;
-
- /*
- * set vccio6 iodomain to also use this framework
- * instead of a special gpio.
- */
- val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16);
- ret = regmap_write(iod->grf, PX30_IO_VSEL, val);
- if (ret < 0)
- dev_warn(iod->dev, "couldn't update vccio6 ctrl\n");
-}
-
-static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
-{
- int ret;
- u32 val;
-
- /* if no flash supply we should leave things alone */
- if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg)
- return;
-
- /*
- * set flash0 iodomain to also use this framework
- * instead of a special gpio.
- */
- val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16);
- ret = regmap_write(iod->grf, RK3288_SOC_CON2, val);
- if (ret < 0)
- dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
-}
-
-static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
-{
- int ret;
- u32 val;
-
- /* if no vccio2 supply we should leave things alone */
- if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg)
- return;
-
- /*
- * set vccio2 iodomain to also use this framework
- * instead of a special gpio.
- */
- val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
- ret = regmap_write(iod->grf, RK3328_SOC_CON4, val);
- if (ret < 0)
- dev_warn(iod->dev, "couldn't update vccio2 vsel ctrl\n");
-}
-
-static void rk3368_iodomain_init(struct rockchip_iodomain *iod)
-{
- int ret;
- u32 val;
-
- /* if no flash supply we should leave things alone */
- if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg)
- return;
-
- /*
- * set flash0 iodomain to also use this framework
- * instead of a special gpio.
- */
- val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16);
- ret = regmap_write(iod->grf, RK3368_SOC_CON15, val);
- if (ret < 0)
- dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
-}
-
-static void rk3399_pmu_iodomain_init(struct rockchip_iodomain *iod)
-{
- int ret;
- u32 val;
-
- /* if no pmu io supply we should leave things alone */
- if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg)
- return;
-
- /*
- * set pmu io iodomain to also use this framework
- * instead of a special gpio.
- */
- val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
- ret = regmap_write(iod->grf, RK3399_PMUGRF_CON0, val);
- if (ret < 0)
- dev_warn(iod->dev, "couldn't update pmu io iodomain ctrl\n");
-}
-
-static const struct rockchip_iodomain_soc_data soc_data_px30 = {
- .grf_offset = 0x180,
- .supply_names = {
- NULL,
- "vccio6",
- "vccio1",
- "vccio2",
- "vccio3",
- "vccio4",
- "vccio5",
- "vccio-oscgpi",
- },
- .init = px30_iodomain_init,
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
- .grf_offset = 0x100,
- .supply_names = {
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "pmuio1",
- "pmuio2",
- },
-};
-
-/*
- * On the rk3188 the io-domains are handled by a shared register with the
- * lower 8 bits being still being continuing drive-strength settings.
- */
-static const struct rockchip_iodomain_soc_data soc_data_rk3188 = {
- .grf_offset = 0x104,
- .supply_names = {
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "ap0",
- "ap1",
- "cif",
- "flash",
- "vccio0",
- "vccio1",
- "lcdc0",
- "lcdc1",
- },
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3228 = {
- .grf_offset = 0x418,
- .supply_names = {
- "vccio1",
- "vccio2",
- "vccio3",
- "vccio4",
- },
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
- .grf_offset = 0x380,
- .supply_names = {
- "lcdc", /* LCDC_VDD */
- "dvp", /* DVPIO_VDD */
- "flash0", /* FLASH0_VDD (emmc) */
- "flash1", /* FLASH1_VDD (sdio1) */
- "wifi", /* APIO3_VDD (sdio0) */
- "bb", /* APIO5_VDD */
- "audio", /* APIO4_VDD */
- "sdcard", /* SDMMC0_VDD (sdmmc) */
- "gpio30", /* APIO1_VDD */
- "gpio1830", /* APIO2_VDD */
- },
- .init = rk3288_iodomain_init,
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
- .grf_offset = 0x410,
- .supply_names = {
- "vccio1",
- "vccio2",
- "vccio3",
- "vccio4",
- "vccio5",
- "vccio6",
- "pmuio",
- },
- .init = rk3328_iodomain_init,
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3368 = {
- .grf_offset = 0x900,
- .supply_names = {
- NULL, /* reserved */
- "dvp", /* DVPIO_VDD */
- "flash0", /* FLASH0_VDD (emmc) */
- "wifi", /* APIO2_VDD (sdio0) */
- NULL,
- "audio", /* APIO3_VDD */
- "sdcard", /* SDMMC0_VDD (sdmmc) */
- "gpio30", /* APIO1_VDD */
- "gpio1830", /* APIO4_VDD (gpujtag) */
- },
- .init = rk3368_iodomain_init,
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu = {
- .grf_offset = 0x100,
- .supply_names = {
- NULL,
- NULL,
- NULL,
- NULL,
- "pmu", /*PMU IO domain*/
- "vop", /*LCDC IO domain*/
- },
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
- .grf_offset = 0xe640,
- .supply_names = {
- "bt656", /* APIO2_VDD */
- "audio", /* APIO5_VDD */
- "sdmmc", /* SDMMC0_VDD */
- "gpio1830", /* APIO4_VDD */
- },
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = {
- .grf_offset = 0x180,
- .supply_names = {
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "pmu1830", /* PMUIO2_VDD */
- },
- .init = rk3399_pmu_iodomain_init,
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rv1108 = {
- .grf_offset = 0x404,
- .supply_names = {
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "vccio1",
- "vccio2",
- "vccio3",
- "vccio5",
- "vccio6",
- },
-
-};
-
-static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
- .grf_offset = 0x104,
- .supply_names = {
- "pmu",
- },
-};
-
-static const struct of_device_id rockchip_iodomain_match[] = {
- {
- .compatible = "rockchip,px30-io-voltage-domain",
- .data = (void *)&soc_data_px30
- },
- {
- .compatible = "rockchip,px30-pmu-io-voltage-domain",
- .data = (void *)&soc_data_px30_pmu
- },
- {
- .compatible = "rockchip,rk3188-io-voltage-domain",
- .data = &soc_data_rk3188
- },
- {
- .compatible = "rockchip,rk3228-io-voltage-domain",
- .data = &soc_data_rk3228
- },
- {
- .compatible = "rockchip,rk3288-io-voltage-domain",
- .data = &soc_data_rk3288
- },
- {
- .compatible = "rockchip,rk3328-io-voltage-domain",
- .data = &soc_data_rk3328
- },
- {
- .compatible = "rockchip,rk3368-io-voltage-domain",
- .data = &soc_data_rk3368
- },
- {
- .compatible = "rockchip,rk3368-pmu-io-voltage-domain",
- .data = &soc_data_rk3368_pmu
- },
- {
- .compatible = "rockchip,rk3399-io-voltage-domain",
- .data = &soc_data_rk3399
- },
- {
- .compatible = "rockchip,rk3399-pmu-io-voltage-domain",
- .data = &soc_data_rk3399_pmu
- },
- {
- .compatible = "rockchip,rv1108-io-voltage-domain",
- .data = &soc_data_rv1108
- },
- {
- .compatible = "rockchip,rv1108-pmu-io-voltage-domain",
- .data = &soc_data_rv1108_pmu
- },
- { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
-
-static int rockchip_iodomain_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- const struct of_device_id *match;
- struct rockchip_iodomain *iod;
- struct device *parent;
- int i, ret = 0;
-
- if (!np)
- return -ENODEV;
-
- iod = devm_kzalloc(&pdev->dev, sizeof(*iod), GFP_KERNEL);
- if (!iod)
- return -ENOMEM;
-
- iod->dev = &pdev->dev;
- platform_set_drvdata(pdev, iod);
-
- match = of_match_node(rockchip_iodomain_match, np);
- iod->soc_data = match->data;
-
- parent = pdev->dev.parent;
- if (parent && parent->of_node) {
- iod->grf = syscon_node_to_regmap(parent->of_node);
- } else {
- dev_dbg(&pdev->dev, "falling back to old binding\n");
- iod->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
- }
-
- if (IS_ERR(iod->grf)) {
- dev_err(&pdev->dev, "couldn't find grf regmap\n");
- return PTR_ERR(iod->grf);
- }
-
- for (i = 0; i < MAX_SUPPLIES; i++) {
- const char *supply_name = iod->soc_data->supply_names[i];
- struct rockchip_iodomain_supply *supply = &iod->supplies[i];
- struct regulator *reg;
- int uV;
-
- if (!supply_name)
- continue;
-
- reg = devm_regulator_get_optional(iod->dev, supply_name);
- if (IS_ERR(reg)) {
- ret = PTR_ERR(reg);
-
- /* If a supply wasn't specified, that's OK */
- if (ret == -ENODEV)
- continue;
- else if (ret != -EPROBE_DEFER)
- dev_err(iod->dev, "couldn't get regulator %s\n",
- supply_name);
- goto unreg_notify;
- }
-
- /* set initial correct value */
- uV = regulator_get_voltage(reg);
-
- /* must be a regulator we can get the voltage of */
- if (uV < 0) {
- dev_err(iod->dev, "Can't determine voltage: %s\n",
- supply_name);
- goto unreg_notify;
- }
-
- if (uV > MAX_VOLTAGE_3_3) {
- dev_crit(iod->dev,
- "%d uV is too high. May damage SoC!\n",
- uV);
- ret = -EINVAL;
- goto unreg_notify;
- }
-
- /* setup our supply */
- supply->idx = i;
- supply->iod = iod;
- supply->reg = reg;
- supply->nb.notifier_call = rockchip_iodomain_notify;
-
- ret = rockchip_iodomain_write(supply, uV);
- if (ret) {
- supply->reg = NULL;
- goto unreg_notify;
- }
-
- /* register regulator notifier */
- ret = regulator_register_notifier(reg, &supply->nb);
- if (ret) {
- dev_err(&pdev->dev,
- "regulator notifier request failed\n");
- supply->reg = NULL;
- goto unreg_notify;
- }
- }
-
- if (iod->soc_data->init)
- iod->soc_data->init(iod);
-
- return 0;
-
-unreg_notify:
- for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
- struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
-
- if (io_supply->reg)
- regulator_unregister_notifier(io_supply->reg,
- &io_supply->nb);
- }
-
- return ret;
-}
-
-static int rockchip_iodomain_remove(struct platform_device *pdev)
-{
- struct rockchip_iodomain *iod = platform_get_drvdata(pdev);
- int i;
-
- for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
- struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
-
- if (io_supply->reg)
- regulator_unregister_notifier(io_supply->reg,
- &io_supply->nb);
- }
-
- return 0;
-}
-
-static struct platform_driver rockchip_iodomain_driver = {
- .probe = rockchip_iodomain_probe,
- .remove = rockchip_iodomain_remove,
- .driver = {
- .name = "rockchip-iodomain",
- .of_match_table = rockchip_iodomain_match,
- },
-};
-
-module_platform_driver(rockchip_iodomain_driver);
-
-MODULE_DESCRIPTION("Rockchip IO-domain driver");
-MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
-MODULE_AUTHOR("Doug Anderson <dianders@chromium.org>");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * OMAP SmartReflex Voltage Control
- *
- * Author: Thara Gopinath <thara@ti.com>
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Thara Gopinath <thara@ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970@ti.com>
- */
-
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/pm_runtime.h>
-#include <linux/power/smartreflex.h>
-
-#define DRIVER_NAME "smartreflex"
-#define SMARTREFLEX_NAME_LEN 32
-#define NVALUE_NAME_LEN 40
-#define SR_DISABLE_TIMEOUT 200
-
-/* sr_list contains all the instances of smartreflex module */
-static LIST_HEAD(sr_list);
-
-static struct omap_sr_class_data *sr_class;
-static struct dentry *sr_dbg_dir;
-
-static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
-{
- __raw_writel(value, (sr->base + offset));
-}
-
-static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
- u32 value)
-{
- u32 reg_val;
-
- /*
- * Smartreflex error config register is special as it contains
- * certain status bits which if written a 1 into means a clear
- * of those bits. So in order to make sure no accidental write of
- * 1 happens to those status bits, do a clear of them in the read
- * value. This mean this API doesn't rewrite values in these bits
- * if they are currently set, but does allow the caller to write
- * those bits.
- */
- if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
- mask |= ERRCONFIG_STATUS_V1_MASK;
- else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
- mask |= ERRCONFIG_VPBOUNDINTST_V2;
-
- reg_val = __raw_readl(sr->base + offset);
- reg_val &= ~mask;
-
- value &= mask;
-
- reg_val |= value;
-
- __raw_writel(reg_val, (sr->base + offset));
-}
-
-static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
-{
- return __raw_readl(sr->base + offset);
-}
-
-static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
-{
- struct omap_sr *sr_info;
-
- if (!voltdm) {
- pr_err("%s: Null voltage domain passed!\n", __func__);
- return ERR_PTR(-EINVAL);
- }
-
- list_for_each_entry(sr_info, &sr_list, node) {
- if (voltdm == sr_info->voltdm)
- return sr_info;
- }
-
- return ERR_PTR(-ENODATA);
-}
-
-static irqreturn_t sr_interrupt(int irq, void *data)
-{
- struct omap_sr *sr_info = data;
- u32 status = 0;
-
- switch (sr_info->ip_type) {
- case SR_TYPE_V1:
- /* Read the status bits */
- status = sr_read_reg(sr_info, ERRCONFIG_V1);
-
- /* Clear them by writing back */
- sr_write_reg(sr_info, ERRCONFIG_V1, status);
- break;
- case SR_TYPE_V2:
- /* Read the status bits */
- status = sr_read_reg(sr_info, IRQSTATUS);
-
- /* Clear them by writing back */
- sr_write_reg(sr_info, IRQSTATUS, status);
- break;
- default:
- dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
- sr_info->ip_type);
- return IRQ_NONE;
- }
-
- if (sr_class->notify)
- sr_class->notify(sr_info, status);
-
- return IRQ_HANDLED;
-}
-
-static void sr_set_clk_length(struct omap_sr *sr)
-{
- struct clk *fck;
- u32 fclk_speed;
-
- /* Try interconnect target module fck first if it already exists */
- fck = clk_get(sr->pdev->dev.parent, "fck");
- if (IS_ERR(fck)) {
- fck = clk_get(&sr->pdev->dev, "fck");
- if (IS_ERR(fck)) {
- dev_err(&sr->pdev->dev,
- "%s: unable to get fck for device %s\n",
- __func__, dev_name(&sr->pdev->dev));
- return;
- }
- }
-
- fclk_speed = clk_get_rate(fck);
- clk_put(fck);
-
- switch (fclk_speed) {
- case 12000000:
- sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
- break;
- case 13000000:
- sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
- break;
- case 19200000:
- sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
- break;
- case 26000000:
- sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
- break;
- case 38400000:
- sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
- break;
- default:
- dev_err(&sr->pdev->dev, "%s: Invalid fclk rate: %d\n",
- __func__, fclk_speed);
- break;
- }
-}
-
-static void sr_start_vddautocomp(struct omap_sr *sr)
-{
- if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
- dev_warn(&sr->pdev->dev,
- "%s: smartreflex class driver not registered\n",
- __func__);
- return;
- }
-
- if (!sr_class->enable(sr))
- sr->autocomp_active = true;
-}
-
-static void sr_stop_vddautocomp(struct omap_sr *sr)
-{
- if (!sr_class || !(sr_class->disable)) {
- dev_warn(&sr->pdev->dev,
- "%s: smartreflex class driver not registered\n",
- __func__);
- return;
- }
-
- if (sr->autocomp_active) {
- sr_class->disable(sr, 1);
- sr->autocomp_active = false;
- }
-}
-
-/*
- * This function handles the initializations which have to be done
- * only when both sr device and class driver regiter has
- * completed. This will be attempted to be called from both sr class
- * driver register and sr device intializtion API's. Only one call
- * will ultimately succeed.
- *
- * Currently this function registers interrupt handler for a particular SR
- * if smartreflex class driver is already registered and has
- * requested for interrupts and the SR interrupt line in present.
- */
-static int sr_late_init(struct omap_sr *sr_info)
-{
- struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
- int ret = 0;
-
- if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
- ret = devm_request_irq(&sr_info->pdev->dev, sr_info->irq,
- sr_interrupt, 0, sr_info->name, sr_info);
- if (ret)
- goto error;
- disable_irq(sr_info->irq);
- }
-
- if (pdata && pdata->enable_on_init)
- sr_start_vddautocomp(sr_info);
-
- return ret;
-
-error:
- list_del(&sr_info->node);
- dev_err(&sr_info->pdev->dev, "%s: ERROR in registering interrupt handler. Smartreflex will not function as desired\n",
- __func__);
-
- return ret;
-}
-
-static void sr_v1_disable(struct omap_sr *sr)
-{
- int timeout = 0;
- int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
- ERRCONFIG_MCUBOUNDINTST;
-
- /* Enable MCUDisableAcknowledge interrupt */
- sr_modify_reg(sr, ERRCONFIG_V1,
- ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
-
- /* SRCONFIG - disable SR */
- sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
- /* Disable all other SR interrupts and clear the status as needed */
- if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
- errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
- sr_modify_reg(sr, ERRCONFIG_V1,
- (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
- ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
- errconf_val);
-
- /*
- * Wait for SR to be disabled.
- * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
- */
- sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
- ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
- timeout);
-
- if (timeout >= SR_DISABLE_TIMEOUT)
- dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
- __func__);
-
- /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
- sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
- ERRCONFIG_MCUDISACKINTST);
-}
-
-static void sr_v2_disable(struct omap_sr *sr)
-{
- int timeout = 0;
-
- /* Enable MCUDisableAcknowledge interrupt */
- sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
-
- /* SRCONFIG - disable SR */
- sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
- /*
- * Disable all other SR interrupts and clear the status
- * write to status register ONLY on need basis - only if status
- * is set.
- */
- if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
- sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
- ERRCONFIG_VPBOUNDINTST_V2);
- else
- sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
- 0x0);
- sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
- IRQENABLE_MCUVALIDINT |
- IRQENABLE_MCUBOUNDSINT));
- sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
- IRQSTATUS_MCVALIDINT |
- IRQSTATUS_MCBOUNDSINT));
-
- /*
- * Wait for SR to be disabled.
- * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
- */
- sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
- IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
- timeout);
-
- if (timeout >= SR_DISABLE_TIMEOUT)
- dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
- __func__);
-
- /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
- sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
- sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
-}
-
-static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
- struct omap_sr *sr, u32 efuse_offs)
-{
- int i;
-
- if (!sr->nvalue_table) {
- dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
- __func__);
- return NULL;
- }
-
- for (i = 0; i < sr->nvalue_count; i++) {
- if (sr->nvalue_table[i].efuse_offs == efuse_offs)
- return &sr->nvalue_table[i];
- }
-
- return NULL;
-}
-
-/* Public Functions */
-
-/**
- * sr_configure_errgen() - Configures the SmartReflex to perform AVS using the
- * error generator module.
- * @sr: SR module to be configured.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the error generator module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_errgen(struct omap_sr *sr)
-{
- u32 sr_config, sr_errconfig, errconfig_offs;
- u32 vpboundint_en, vpboundint_st;
- u32 senp_en = 0, senn_en = 0;
- u8 senp_shift, senn_shift;
-
- if (!sr) {
- pr_warn("%s: NULL omap_sr from %pS\n",
- __func__, (void *)_RET_IP_);
- return -EINVAL;
- }
-
- if (!sr->clk_length)
- sr_set_clk_length(sr);
-
- senp_en = sr->senp_mod;
- senn_en = sr->senn_mod;
-
- sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
- SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
-
- switch (sr->ip_type) {
- case SR_TYPE_V1:
- sr_config |= SRCONFIG_DELAYCTRL;
- senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
- senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
- errconfig_offs = ERRCONFIG_V1;
- vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
- vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
- break;
- case SR_TYPE_V2:
- senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
- senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
- errconfig_offs = ERRCONFIG_V2;
- vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
- vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
- break;
- default:
- dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
- __func__);
- return -EINVAL;
- }
-
- sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
- sr_write_reg(sr, SRCONFIG, sr_config);
- sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
- (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
- (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT);
- sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
- SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
- sr_errconfig);
-
- /* Enabling the interrupts if the ERROR module is used */
- sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
- vpboundint_en);
-
- return 0;
-}
-
-/**
- * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
- * @sr: SR module to be configured.
- *
- * This API is to be called from the smartreflex class driver to
- * disable the error generator module inside the smartreflex module.
- *
- * Returns 0 on success and error value in case of failure.
- */
-int sr_disable_errgen(struct omap_sr *sr)
-{
- u32 errconfig_offs;
- u32 vpboundint_en, vpboundint_st;
-
- if (!sr) {
- pr_warn("%s: NULL omap_sr from %pS\n",
- __func__, (void *)_RET_IP_);
- return -EINVAL;
- }
-
- switch (sr->ip_type) {
- case SR_TYPE_V1:
- errconfig_offs = ERRCONFIG_V1;
- vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
- vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
- break;
- case SR_TYPE_V2:
- errconfig_offs = ERRCONFIG_V2;
- vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
- vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
- break;
- default:
- dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
- __func__);
- return -EINVAL;
- }
-
- /* Disable the Sensor and errorgen */
- sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
-
- /*
- * Disable the interrupts of ERROR module
- * NOTE: modify is a read, modify,write - an implicit OCP barrier
- * which is required is present here - sequencing is critical
- * at this point (after errgen is disabled, vpboundint disable)
- */
- sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
-
- return 0;
-}
-
-/**
- * sr_configure_minmax() - Configures the SmartReflex to perform AVS using the
- * minmaxavg module.
- * @sr: SR module to be configured.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the minmaxavg module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_minmax(struct omap_sr *sr)
-{
- u32 sr_config, sr_avgwt;
- u32 senp_en = 0, senn_en = 0;
- u8 senp_shift, senn_shift;
-
- if (!sr) {
- pr_warn("%s: NULL omap_sr from %pS\n",
- __func__, (void *)_RET_IP_);
- return -EINVAL;
- }
-
- if (!sr->clk_length)
- sr_set_clk_length(sr);
-
- senp_en = sr->senp_mod;
- senn_en = sr->senn_mod;
-
- sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
- SRCONFIG_SENENABLE |
- (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
-
- switch (sr->ip_type) {
- case SR_TYPE_V1:
- sr_config |= SRCONFIG_DELAYCTRL;
- senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
- senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
- break;
- case SR_TYPE_V2:
- senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
- senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
- break;
- default:
- dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
- __func__);
- return -EINVAL;
- }
-
- sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
- sr_write_reg(sr, SRCONFIG, sr_config);
- sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
- (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
- sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
-
- /*
- * Enabling the interrupts if MINMAXAVG module is used.
- * TODO: check if all the interrupts are mandatory
- */
- switch (sr->ip_type) {
- case SR_TYPE_V1:
- sr_modify_reg(sr, ERRCONFIG_V1,
- (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
- ERRCONFIG_MCUBOUNDINTEN),
- (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
- ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
- ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
- break;
- case SR_TYPE_V2:
- sr_write_reg(sr, IRQSTATUS,
- IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
- IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
- sr_write_reg(sr, IRQENABLE_SET,
- IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
- IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
- break;
- default:
- dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
- __func__);
- return -EINVAL;
- }
-
- return 0;
-}
-
-/**
- * sr_enable() - Enables the smartreflex module.
- * @sr: pointer to which the SR module to be configured belongs to.
- * @volt: The voltage at which the Voltage domain associated with
- * the smartreflex module is operating at.
- * This is required only to program the correct Ntarget value.
- *
- * This API is to be called from the smartreflex class driver to
- * enable a smartreflex module. Returns 0 on success. Returns error
- * value if the voltage passed is wrong or if ntarget value is wrong.
- */
-int sr_enable(struct omap_sr *sr, unsigned long volt)
-{
- struct omap_volt_data *volt_data;
- struct omap_sr_nvalue_table *nvalue_row;
- int ret;
-
- if (!sr) {
- pr_warn("%s: NULL omap_sr from %pS\n",
- __func__, (void *)_RET_IP_);
- return -EINVAL;
- }
-
- volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
-
- if (IS_ERR(volt_data)) {
- dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table for nominal voltage %ld\n",
- __func__, volt);
- return PTR_ERR(volt_data);
- }
-
- nvalue_row = sr_retrieve_nvalue_row(sr, volt_data->sr_efuse_offs);
-
- if (!nvalue_row) {
- dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
- __func__, volt);
- return -ENODATA;
- }
-
- /* errminlimit is opp dependent and hence linked to voltage */
- sr->err_minlimit = nvalue_row->errminlimit;
-
- pm_runtime_get_sync(&sr->pdev->dev);
-
- /* Check if SR is already enabled. If yes do nothing */
- if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
- return 0;
-
- /* Configure SR */
- ret = sr_class->configure(sr);
- if (ret)
- return ret;
-
- sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
-
- /* SRCONFIG - enable SR */
- sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
- return 0;
-}
-
-/**
- * sr_disable() - Disables the smartreflex module.
- * @sr: pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable a smartreflex module.
- */
-void sr_disable(struct omap_sr *sr)
-{
- if (!sr) {
- pr_warn("%s: NULL omap_sr from %pS\n",
- __func__, (void *)_RET_IP_);
- return;
- }
-
- /* Check if SR clocks are already disabled. If yes do nothing */
- if (pm_runtime_suspended(&sr->pdev->dev))
- return;
-
- /*
- * Disable SR if only it is indeed enabled. Else just
- * disable the clocks.
- */
- if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
- switch (sr->ip_type) {
- case SR_TYPE_V1:
- sr_v1_disable(sr);
- break;
- case SR_TYPE_V2:
- sr_v2_disable(sr);
- break;
- default:
- dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
- sr->ip_type);
- }
- }
-
- pm_runtime_put_sync_suspend(&sr->pdev->dev);
-}
-
-/**
- * sr_register_class() - API to register a smartreflex class parameters.
- * @class_data: The structure containing various sr class specific data.
- *
- * This API is to be called by the smartreflex class driver to register itself
- * with the smartreflex driver during init. Returns 0 on success else the
- * error value.
- */
-int sr_register_class(struct omap_sr_class_data *class_data)
-{
- struct omap_sr *sr_info;
-
- if (!class_data) {
- pr_warn("%s:, Smartreflex class data passed is NULL\n",
- __func__);
- return -EINVAL;
- }
-
- if (sr_class) {
- pr_warn("%s: Smartreflex class driver already registered\n",
- __func__);
- return -EBUSY;
- }
-
- sr_class = class_data;
-
- /*
- * Call into late init to do initializations that require
- * both sr driver and sr class driver to be initiallized.
- */
- list_for_each_entry(sr_info, &sr_list, node)
- sr_late_init(sr_info);
-
- return 0;
-}
-
-/**
- * omap_sr_enable() - API to enable SR clocks and to call into the
- * registered smartreflex class enable API.
- * @voltdm: VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to enable
- * a particular smartreflex module. This API will do the initial
- * configurations to turn on the smartreflex module and in turn call
- * into the registered smartreflex class enable API.
- */
-void omap_sr_enable(struct voltagedomain *voltdm)
-{
- struct omap_sr *sr = _sr_lookup(voltdm);
-
- if (IS_ERR(sr)) {
- pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
- return;
- }
-
- if (!sr->autocomp_active)
- return;
-
- if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
- dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
- __func__);
- return;
- }
-
- sr_class->enable(sr);
-}
-
-/**
- * omap_sr_disable() - API to disable SR without resetting the voltage
- * processor voltage
- * @voltdm: VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable not to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable(struct voltagedomain *voltdm)
-{
- struct omap_sr *sr = _sr_lookup(voltdm);
-
- if (IS_ERR(sr)) {
- pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
- return;
- }
-
- if (!sr->autocomp_active)
- return;
-
- if (!sr_class || !(sr_class->disable)) {
- dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
- __func__);
- return;
- }
-
- sr_class->disable(sr, 0);
-}
-
-/**
- * omap_sr_disable_reset_volt() - API to disable SR and reset the
- * voltage processor voltage
- * @voltdm: VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
-{
- struct omap_sr *sr = _sr_lookup(voltdm);
-
- if (IS_ERR(sr)) {
- pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
- return;
- }
-
- if (!sr->autocomp_active)
- return;
-
- if (!sr_class || !(sr_class->disable)) {
- dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
- __func__);
- return;
- }
-
- sr_class->disable(sr, 1);
-}
-
-/* PM Debug FS entries to enable and disable smartreflex. */
-static int omap_sr_autocomp_show(void *data, u64 *val)
-{
- struct omap_sr *sr_info = data;
-
- if (!sr_info) {
- pr_warn("%s: omap_sr struct not found\n", __func__);
- return -EINVAL;
- }
-
- *val = sr_info->autocomp_active;
-
- return 0;
-}
-
-static int omap_sr_autocomp_store(void *data, u64 val)
-{
- struct omap_sr *sr_info = data;
-
- if (!sr_info) {
- pr_warn("%s: omap_sr struct not found\n", __func__);
- return -EINVAL;
- }
-
- /* Sanity check */
- if (val > 1) {
- pr_warn("%s: Invalid argument %lld\n", __func__, val);
- return -EINVAL;
- }
-
- /* control enable/disable only if there is a delta in value */
- if (sr_info->autocomp_active != val) {
- if (!val)
- sr_stop_vddautocomp(sr_info);
- else
- sr_start_vddautocomp(sr_info);
- }
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
- omap_sr_autocomp_store, "%llu\n");
-
-static int omap_sr_probe(struct platform_device *pdev)
-{
- struct omap_sr *sr_info;
- struct omap_sr_data *pdata = pdev->dev.platform_data;
- struct resource *mem, *irq;
- struct dentry *nvalue_dir;
- int i, ret = 0;
-
- sr_info = devm_kzalloc(&pdev->dev, sizeof(struct omap_sr), GFP_KERNEL);
- if (!sr_info)
- return -ENOMEM;
-
- sr_info->name = devm_kzalloc(&pdev->dev,
- SMARTREFLEX_NAME_LEN, GFP_KERNEL);
- if (!sr_info->name)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, sr_info);
-
- if (!pdata) {
- dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
- return -EINVAL;
- }
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- sr_info->base = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(sr_info->base)) {
- dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
- return PTR_ERR(sr_info->base);
- }
-
- irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-
- pm_runtime_enable(&pdev->dev);
- pm_runtime_irq_safe(&pdev->dev);
-
- snprintf(sr_info->name, SMARTREFLEX_NAME_LEN, "%s", pdata->name);
-
- sr_info->pdev = pdev;
- sr_info->srid = pdev->id;
- sr_info->voltdm = pdata->voltdm;
- sr_info->nvalue_table = pdata->nvalue_table;
- sr_info->nvalue_count = pdata->nvalue_count;
- sr_info->senn_mod = pdata->senn_mod;
- sr_info->senp_mod = pdata->senp_mod;
- sr_info->err_weight = pdata->err_weight;
- sr_info->err_maxlimit = pdata->err_maxlimit;
- sr_info->accum_data = pdata->accum_data;
- sr_info->senn_avgweight = pdata->senn_avgweight;
- sr_info->senp_avgweight = pdata->senp_avgweight;
- sr_info->autocomp_active = false;
- sr_info->ip_type = pdata->ip_type;
-
- if (irq)
- sr_info->irq = irq->start;
-
- sr_set_clk_length(sr_info);
-
- list_add(&sr_info->node, &sr_list);
-
- ret = pm_runtime_get_sync(&pdev->dev);
- if (ret < 0) {
- pm_runtime_put_noidle(&pdev->dev);
- goto err_list_del;
- }
-
- /*
- * Call into late init to do initializations that require
- * both sr driver and sr class driver to be initiallized.
- */
- if (sr_class) {
- ret = sr_late_init(sr_info);
- if (ret) {
- pr_warn("%s: Error in SR late init\n", __func__);
- goto err_list_del;
- }
- }
-
- dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
- if (!sr_dbg_dir)
- sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-
- sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
-
- debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, sr_info->dbg_dir,
- sr_info, &pm_sr_fops);
- debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
- &sr_info->err_weight);
- debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
- &sr_info->err_maxlimit);
-
- nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-
- if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
- dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
- __func__, sr_info->name);
-
- ret = -ENODATA;
- goto err_debugfs;
- }
-
- for (i = 0; i < sr_info->nvalue_count; i++) {
- char name[NVALUE_NAME_LEN + 1];
-
- snprintf(name, sizeof(name), "volt_%lu",
- sr_info->nvalue_table[i].volt_nominal);
- debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
- &(sr_info->nvalue_table[i].nvalue));
- snprintf(name, sizeof(name), "errminlimit_%lu",
- sr_info->nvalue_table[i].volt_nominal);
- debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
- &(sr_info->nvalue_table[i].errminlimit));
-
- }
-
- pm_runtime_put_sync(&pdev->dev);
-
- return ret;
-
-err_debugfs:
- debugfs_remove_recursive(sr_info->dbg_dir);
-err_list_del:
- list_del(&sr_info->node);
-
- pm_runtime_put_sync(&pdev->dev);
-
- return ret;
-}
-
-static int omap_sr_remove(struct platform_device *pdev)
-{
- struct omap_sr_data *pdata = pdev->dev.platform_data;
- struct omap_sr *sr_info;
-
- if (!pdata) {
- dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
- return -EINVAL;
- }
-
- sr_info = _sr_lookup(pdata->voltdm);
- if (IS_ERR(sr_info)) {
- dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
- __func__);
- return PTR_ERR(sr_info);
- }
-
- if (sr_info->autocomp_active)
- sr_stop_vddautocomp(sr_info);
- debugfs_remove_recursive(sr_info->dbg_dir);
-
- pm_runtime_disable(&pdev->dev);
- list_del(&sr_info->node);
- return 0;
-}
-
-static void omap_sr_shutdown(struct platform_device *pdev)
-{
- struct omap_sr_data *pdata = pdev->dev.platform_data;
- struct omap_sr *sr_info;
-
- if (!pdata) {
- dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
- return;
- }
-
- sr_info = _sr_lookup(pdata->voltdm);
- if (IS_ERR(sr_info)) {
- dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
- __func__);
- return;
- }
-
- if (sr_info->autocomp_active)
- sr_stop_vddautocomp(sr_info);
-
- return;
-}
-
-static const struct of_device_id omap_sr_match[] = {
- { .compatible = "ti,omap3-smartreflex-core", },
- { .compatible = "ti,omap3-smartreflex-mpu-iva", },
- { .compatible = "ti,omap4-smartreflex-core", },
- { .compatible = "ti,omap4-smartreflex-mpu", },
- { .compatible = "ti,omap4-smartreflex-iva", },
- { },
-};
-MODULE_DEVICE_TABLE(of, omap_sr_match);
-
-static struct platform_driver smartreflex_driver = {
- .probe = omap_sr_probe,
- .remove = omap_sr_remove,
- .shutdown = omap_sr_shutdown,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = omap_sr_match,
- },
-};
-
-static int __init sr_init(void)
-{
- int ret = 0;
-
- ret = platform_driver_register(&smartreflex_driver);
- if (ret) {
- pr_err("%s: platform driver register failed for SR\n",
- __func__);
- return ret;
- }
-
- return 0;
-}
-late_initcall(sr_init);
-
-static void __exit sr_exit(void)
-{
- platform_driver_unregister(&smartreflex_driver);
-}
-module_exit(sr_exit);
-
-MODULE_DESCRIPTION("OMAP Smartreflex Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_AUTHOR("Texas Instruments Inc");
resource on a RPM-hardened platform must use this database to get
SoC specific identifier and information for the shared resources.
+config QCOM_CPR
+ tristate "QCOM Core Power Reduction (CPR) support"
+ depends on ARCH_QCOM && HAS_IOMEM
+ select PM_OPP
+ select REGMAP
+ help
+ Say Y here to enable support for the CPR hardware found on Qualcomm
+ SoCs like QCS404.
+
+ This driver populates CPU OPPs tables and makes adjustments to the
+ tables based on feedback from the CPR hardware. If you want to do
+ CPUfrequency scaling say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called qcom-cpr
+
config QCOM_GENI_SE
tristate "QCOM GENI Serial Engine Driver"
depends on ARCH_QCOM || COMPILE_TEST
obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o
obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
+obj-$(CONFIG_QCOM_CPR) += cpr.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/nvmem-consumer.h>
+
+/* Register Offsets for RB-CPR and Bit Definitions */
+
+/* RBCPR Version Register */
+#define REG_RBCPR_VERSION 0
+#define RBCPR_VER_2 0x02
+#define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0)
+
+/* RBCPR Gate Count and Target Registers */
+#define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n))
+
+#define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
+#define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)
+#define RBCPR_GCNT_TARGET_GCNT_SHIFT 12
+#define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)
+
+/* RBCPR Timer Control */
+#define REG_RBCPR_TIMER_INTERVAL 0x44
+#define REG_RBIF_TIMER_ADJUST 0x4c
+
+#define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)
+#define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0
+#define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)
+#define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
+#define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)
+#define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
+
+/* RBCPR Config Register */
+#define REG_RBIF_LIMIT 0x48
+#define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)
+#define RBIF_LIMIT_CEILING_SHIFT 6
+#define RBIF_LIMIT_FLOOR_BITS 6
+#define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)
+
+#define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK
+#define RBIF_LIMIT_FLOOR_DEFAULT 0
+
+#define REG_RBIF_SW_VLEVEL 0x94
+#define RBIF_SW_VLEVEL_DEFAULT 0x20
+
+#define REG_RBCPR_STEP_QUOT 0x80
+#define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)
+#define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)
+#define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
+
+/* RBCPR Control Register */
+#define REG_RBCPR_CTL 0x90
+
+#define RBCPR_CTL_LOOP_EN BIT(0)
+#define RBCPR_CTL_TIMER_EN BIT(3)
+#define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5)
+#define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6)
+#define RBCPR_CTL_COUNT_MODE BIT(10)
+#define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)
+#define RBCPR_CTL_UP_THRESHOLD_SHIFT 24
+#define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)
+#define RBCPR_CTL_DN_THRESHOLD_SHIFT 28
+
+/* RBCPR Ack/Nack Response */
+#define REG_RBIF_CONT_ACK_CMD 0x98
+#define REG_RBIF_CONT_NACK_CMD 0x9c
+
+/* RBCPR Result status Register */
+#define REG_RBCPR_RESULT_0 0xa0
+
+#define RBCPR_RESULT0_BUSY_SHIFT 19
+#define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT)
+#define RBCPR_RESULT0_ERROR_LT0_SHIFT 18
+#define RBCPR_RESULT0_ERROR_SHIFT 6
+#define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)
+#define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
+#define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
+#define RBCPR_RESULT0_STEP_UP_SHIFT 1
+
+/* RBCPR Interrupt Control Register */
+#define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n))
+#define REG_RBIF_IRQ_CLEAR 0x110
+#define REG_RBIF_IRQ_STATUS 0x114
+
+#define CPR_INT_DONE BIT(0)
+#define CPR_INT_MIN BIT(1)
+#define CPR_INT_DOWN BIT(2)
+#define CPR_INT_MID BIT(3)
+#define CPR_INT_UP BIT(4)
+#define CPR_INT_MAX BIT(5)
+#define CPR_INT_CLAMP BIT(6)
+#define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
+ CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
+#define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
+
+#define CPR_NUM_RING_OSC 8
+
+/* CPR eFuse parameters */
+#define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
+
+#define CPR_FUSE_MIN_QUOT_DIFF 50
+
+#define FUSE_REVISION_UNKNOWN (-1)
+
+enum voltage_change_dir {
+ NO_CHANGE,
+ DOWN,
+ UP,
+};
+
+struct cpr_fuse {
+ char *ring_osc;
+ char *init_voltage;
+ char *quotient;
+ char *quotient_offset;
+};
+
+struct fuse_corner_data {
+ int ref_uV;
+ int max_uV;
+ int min_uV;
+ int max_volt_scale;
+ int max_quot_scale;
+ /* fuse quot */
+ int quot_offset;
+ int quot_scale;
+ int quot_adjust;
+ /* fuse quot_offset */
+ int quot_offset_scale;
+ int quot_offset_adjust;
+};
+
+struct cpr_fuses {
+ int init_voltage_step;
+ int init_voltage_width;
+ struct fuse_corner_data *fuse_corner_data;
+};
+
+struct corner_data {
+ unsigned int fuse_corner;
+ unsigned long freq;
+};
+
+struct cpr_desc {
+ unsigned int num_fuse_corners;
+ int min_diff_quot;
+ int *step_quot;
+
+ unsigned int timer_delay_us;
+ unsigned int timer_cons_up;
+ unsigned int timer_cons_down;
+ unsigned int up_threshold;
+ unsigned int down_threshold;
+ unsigned int idle_clocks;
+ unsigned int gcnt_us;
+ unsigned int vdd_apc_step_up_limit;
+ unsigned int vdd_apc_step_down_limit;
+ unsigned int clamp_timer_interval;
+
+ struct cpr_fuses cpr_fuses;
+ bool reduce_to_fuse_uV;
+ bool reduce_to_corner_uV;
+};
+
+struct acc_desc {
+ unsigned int enable_reg;
+ u32 enable_mask;
+
+ struct reg_sequence *config;
+ struct reg_sequence *settings;
+ int num_regs_per_fuse;
+};
+
+struct cpr_acc_desc {
+ const struct cpr_desc *cpr_desc;
+ const struct acc_desc *acc_desc;
+};
+
+struct fuse_corner {
+ int min_uV;
+ int max_uV;
+ int uV;
+ int quot;
+ int step_quot;
+ const struct reg_sequence *accs;
+ int num_accs;
+ unsigned long max_freq;
+ u8 ring_osc_idx;
+};
+
+struct corner {
+ int min_uV;
+ int max_uV;
+ int uV;
+ int last_uV;
+ int quot_adjust;
+ u32 save_ctl;
+ u32 save_irq;
+ unsigned long freq;
+ struct fuse_corner *fuse_corner;
+};
+
+struct cpr_drv {
+ unsigned int num_corners;
+ unsigned int ref_clk_khz;
+
+ struct generic_pm_domain pd;
+ struct device *dev;
+ struct device *attached_cpu_dev;
+ struct mutex lock;
+ void __iomem *base;
+ struct corner *corner;
+ struct regulator *vdd_apc;
+ struct clk *cpu_clk;
+ struct regmap *tcsr;
+ bool loop_disabled;
+ u32 gcnt;
+ unsigned long flags;
+
+ struct fuse_corner *fuse_corners;
+ struct corner *corners;
+
+ const struct cpr_desc *desc;
+ const struct acc_desc *acc_desc;
+ const struct cpr_fuse *cpr_fuses;
+
+ struct dentry *debugfs;
+};
+
+static bool cpr_is_allowed(struct cpr_drv *drv)
+{
+ return !drv->loop_disabled;
+}
+
+static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
+{
+ writel_relaxed(value, drv->base + offset);
+}
+
+static u32 cpr_read(struct cpr_drv *drv, u32 offset)
+{
+ return readl_relaxed(drv->base + offset);
+}
+
+static void
+cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
+{
+ u32 val;
+
+ val = readl_relaxed(drv->base + offset);
+ val &= ~mask;
+ val |= value & mask;
+ writel_relaxed(val, drv->base + offset);
+}
+
+static void cpr_irq_clr(struct cpr_drv *drv)
+{
+ cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
+}
+
+static void cpr_irq_clr_nack(struct cpr_drv *drv)
+{
+ cpr_irq_clr(drv);
+ cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
+}
+
+static void cpr_irq_clr_ack(struct cpr_drv *drv)
+{
+ cpr_irq_clr(drv);
+ cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
+}
+
+static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
+{
+ cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
+}
+
+static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
+{
+ cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
+}
+
+static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
+{
+ u32 val, mask;
+ const struct cpr_desc *desc = drv->desc;
+
+ /* Program Consecutive Up & Down */
+ val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
+ val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
+ mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
+ cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
+ cpr_masked_write(drv, REG_RBCPR_CTL,
+ RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
+ RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
+ corner->save_ctl);
+ cpr_irq_set(drv, corner->save_irq);
+
+ if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
+ val = RBCPR_CTL_LOOP_EN;
+ else
+ val = 0;
+ cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
+}
+
+static void cpr_ctl_disable(struct cpr_drv *drv)
+{
+ cpr_irq_set(drv, 0);
+ cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
+ RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
+ cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
+ RBIF_TIMER_ADJ_CONS_UP_MASK |
+ RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
+ cpr_irq_clr(drv);
+ cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
+ cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
+ cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
+}
+
+static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
+{
+ u32 reg_val;
+
+ reg_val = cpr_read(drv, REG_RBCPR_CTL);
+ return reg_val & RBCPR_CTL_LOOP_EN;
+}
+
+static bool cpr_ctl_is_busy(struct cpr_drv *drv)
+{
+ u32 reg_val;
+
+ reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
+ return reg_val & RBCPR_RESULT0_BUSY_MASK;
+}
+
+static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
+{
+ corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
+ corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
+}
+
+static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
+{
+ u32 gcnt, ctl, irq, ro_sel, step_quot;
+ struct fuse_corner *fuse = corner->fuse_corner;
+ const struct cpr_desc *desc = drv->desc;
+ int i;
+
+ ro_sel = fuse->ring_osc_idx;
+ gcnt = drv->gcnt;
+ gcnt |= fuse->quot - corner->quot_adjust;
+
+ /* Program the step quotient and idle clocks */
+ step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
+ step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
+ cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
+
+ /* Clear the target quotient value and gate count of all ROs */
+ for (i = 0; i < CPR_NUM_RING_OSC; i++)
+ cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
+
+ cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
+ ctl = corner->save_ctl;
+ cpr_write(drv, REG_RBCPR_CTL, ctl);
+ irq = corner->save_irq;
+ cpr_irq_set(drv, irq);
+ dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt,
+ ctl, irq);
+}
+
+static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
+ struct fuse_corner *end)
+{
+ if (f == end)
+ return;
+
+ if (f < end) {
+ for (f += 1; f <= end; f++)
+ regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
+ } else {
+ for (f -= 1; f >= end; f--)
+ regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
+ }
+}
+
+static int cpr_pre_voltage(struct cpr_drv *drv,
+ struct fuse_corner *fuse_corner,
+ enum voltage_change_dir dir)
+{
+ struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
+
+ if (drv->tcsr && dir == DOWN)
+ cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
+
+ return 0;
+}
+
+static int cpr_post_voltage(struct cpr_drv *drv,
+ struct fuse_corner *fuse_corner,
+ enum voltage_change_dir dir)
+{
+ struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
+
+ if (drv->tcsr && dir == UP)
+ cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
+
+ return 0;
+}
+
+static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
+ int new_uV, enum voltage_change_dir dir)
+{
+ int ret;
+ struct fuse_corner *fuse_corner = corner->fuse_corner;
+
+ ret = cpr_pre_voltage(drv, fuse_corner, dir);
+ if (ret)
+ return ret;
+
+ ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
+ if (ret) {
+ dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
+ new_uV);
+ return ret;
+ }
+
+ ret = cpr_post_voltage(drv, fuse_corner, dir);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv)
+{
+ return drv->corner ? drv->corner - drv->corners + 1 : 0;
+}
+
+static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
+{
+ u32 val, error_steps, reg_mask;
+ int last_uV, new_uV, step_uV, ret;
+ struct corner *corner;
+ const struct cpr_desc *desc = drv->desc;
+
+ if (dir != UP && dir != DOWN)
+ return 0;
+
+ step_uV = regulator_get_linear_step(drv->vdd_apc);
+ if (!step_uV)
+ return -EINVAL;
+
+ corner = drv->corner;
+
+ val = cpr_read(drv, REG_RBCPR_RESULT_0);
+
+ error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
+ error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
+ last_uV = corner->last_uV;
+
+ if (dir == UP) {
+ if (desc->clamp_timer_interval &&
+ error_steps < desc->up_threshold) {
+ /*
+ * Handle the case where another measurement started
+ * after the interrupt was triggered due to a core
+ * exiting from power collapse.
+ */
+ error_steps = max(desc->up_threshold,
+ desc->vdd_apc_step_up_limit);
+ }
+
+ if (last_uV >= corner->max_uV) {
+ cpr_irq_clr_nack(drv);
+
+ /* Maximize the UP threshold */
+ reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
+ reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+ val = reg_mask;
+ cpr_ctl_modify(drv, reg_mask, val);
+
+ /* Disable UP interrupt */
+ cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
+
+ return 0;
+ }
+
+ if (error_steps > desc->vdd_apc_step_up_limit)
+ error_steps = desc->vdd_apc_step_up_limit;
+
+ /* Calculate new voltage */
+ new_uV = last_uV + error_steps * step_uV;
+ new_uV = min(new_uV, corner->max_uV);
+
+ dev_dbg(drv->dev,
+ "UP: -> new_uV: %d last_uV: %d perf state: %u\n",
+ new_uV, last_uV, cpr_get_cur_perf_state(drv));
+ } else {
+ if (desc->clamp_timer_interval &&
+ error_steps < desc->down_threshold) {
+ /*
+ * Handle the case where another measurement started
+ * after the interrupt was triggered due to a core
+ * exiting from power collapse.
+ */
+ error_steps = max(desc->down_threshold,
+ desc->vdd_apc_step_down_limit);
+ }
+
+ if (last_uV <= corner->min_uV) {
+ cpr_irq_clr_nack(drv);
+
+ /* Enable auto nack down */
+ reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+ val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+
+ cpr_ctl_modify(drv, reg_mask, val);
+
+ /* Disable DOWN interrupt */
+ cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
+
+ return 0;
+ }
+
+ if (error_steps > desc->vdd_apc_step_down_limit)
+ error_steps = desc->vdd_apc_step_down_limit;
+
+ /* Calculate new voltage */
+ new_uV = last_uV - error_steps * step_uV;
+ new_uV = max(new_uV, corner->min_uV);
+
+ dev_dbg(drv->dev,
+ "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n",
+ new_uV, last_uV, cpr_get_cur_perf_state(drv));
+ }
+
+ ret = cpr_scale_voltage(drv, corner, new_uV, dir);
+ if (ret) {
+ cpr_irq_clr_nack(drv);
+ return ret;
+ }
+ drv->corner->last_uV = new_uV;
+
+ if (dir == UP) {
+ /* Disable auto nack down */
+ reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+ val = 0;
+ } else {
+ /* Restore default threshold for UP */
+ reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
+ reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+ val = desc->up_threshold;
+ val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+ }
+
+ cpr_ctl_modify(drv, reg_mask, val);
+
+ /* Re-enable default interrupts */
+ cpr_irq_set(drv, CPR_INT_DEFAULT);
+
+ /* Ack */
+ cpr_irq_clr_ack(drv);
+
+ return 0;
+}
+
+static irqreturn_t cpr_irq_handler(int irq, void *dev)
+{
+ struct cpr_drv *drv = dev;
+ const struct cpr_desc *desc = drv->desc;
+ irqreturn_t ret = IRQ_HANDLED;
+ u32 val;
+
+ mutex_lock(&drv->lock);
+
+ val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+ if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
+ val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+
+ dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
+
+ if (!cpr_ctl_is_enabled(drv)) {
+ dev_dbg(drv->dev, "CPR is disabled\n");
+ ret = IRQ_NONE;
+ } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) {
+ dev_dbg(drv->dev, "CPR measurement is not ready\n");
+ } else if (!cpr_is_allowed(drv)) {
+ val = cpr_read(drv, REG_RBCPR_CTL);
+ dev_err_ratelimited(drv->dev,
+ "Interrupt broken? RBCPR_CTL = %#02x\n",
+ val);
+ ret = IRQ_NONE;
+ } else {
+ /*
+ * Following sequence of handling is as per each IRQ's
+ * priority
+ */
+ if (val & CPR_INT_UP) {
+ cpr_scale(drv, UP);
+ } else if (val & CPR_INT_DOWN) {
+ cpr_scale(drv, DOWN);
+ } else if (val & CPR_INT_MIN) {
+ cpr_irq_clr_nack(drv);
+ } else if (val & CPR_INT_MAX) {
+ cpr_irq_clr_nack(drv);
+ } else if (val & CPR_INT_MID) {
+ /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
+ dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
+ } else {
+ dev_dbg(drv->dev,
+ "IRQ occurred for unknown flag (%#08x)\n", val);
+ }
+
+ /* Save register values for the corner */
+ cpr_corner_save(drv, drv->corner);
+ }
+
+ mutex_unlock(&drv->lock);
+
+ return ret;
+}
+
+static int cpr_enable(struct cpr_drv *drv)
+{
+ int ret;
+
+ ret = regulator_enable(drv->vdd_apc);
+ if (ret)
+ return ret;
+
+ mutex_lock(&drv->lock);
+
+ if (cpr_is_allowed(drv) && drv->corner) {
+ cpr_irq_clr(drv);
+ cpr_corner_restore(drv, drv->corner);
+ cpr_ctl_enable(drv, drv->corner);
+ }
+
+ mutex_unlock(&drv->lock);
+
+ return 0;
+}
+
+static int cpr_disable(struct cpr_drv *drv)
+{
+ mutex_lock(&drv->lock);
+
+ if (cpr_is_allowed(drv)) {
+ cpr_ctl_disable(drv);
+ cpr_irq_clr(drv);
+ }
+
+ mutex_unlock(&drv->lock);
+
+ return regulator_disable(drv->vdd_apc);
+}
+
+static int cpr_config(struct cpr_drv *drv)
+{
+ int i;
+ u32 val, gcnt;
+ struct corner *corner;
+ const struct cpr_desc *desc = drv->desc;
+
+ /* Disable interrupt and CPR */
+ cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
+ cpr_write(drv, REG_RBCPR_CTL, 0);
+
+ /* Program the default HW ceiling, floor and vlevel */
+ val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
+ << RBIF_LIMIT_CEILING_SHIFT;
+ val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
+ cpr_write(drv, REG_RBIF_LIMIT, val);
+ cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
+
+ /*
+ * Clear the target quotient value and gate count of all
+ * ring oscillators
+ */
+ for (i = 0; i < CPR_NUM_RING_OSC; i++)
+ cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
+
+ /* Init and save gcnt */
+ gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000;
+ gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
+ gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
+ drv->gcnt = gcnt;
+
+ /* Program the delay count for the timer */
+ val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
+ cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
+ dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
+ desc->timer_delay_us);
+
+ /* Program Consecutive Up & Down */
+ val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
+ val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
+ val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
+ cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
+
+ /* Program the control register */
+ val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
+ val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
+ val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
+ val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
+ cpr_write(drv, REG_RBCPR_CTL, val);
+
+ for (i = 0; i < drv->num_corners; i++) {
+ corner = &drv->corners[i];
+ corner->save_ctl = val;
+ corner->save_irq = CPR_INT_DEFAULT;
+ }
+
+ cpr_irq_set(drv, CPR_INT_DEFAULT);
+
+ val = cpr_read(drv, REG_RBCPR_VERSION);
+ if (val <= RBCPR_VER_2)
+ drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
+
+ return 0;
+}
+
+static int cpr_set_performance_state(struct generic_pm_domain *domain,
+ unsigned int state)
+{
+ struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+ struct corner *corner, *end;
+ enum voltage_change_dir dir;
+ int ret = 0, new_uV;
+
+ mutex_lock(&drv->lock);
+
+ dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n",
+ __func__, state, cpr_get_cur_perf_state(drv));
+
+ /*
+ * Determine new corner we're going to.
+ * Remove one since lowest performance state is 1.
+ */
+ corner = drv->corners + state - 1;
+ end = &drv->corners[drv->num_corners - 1];
+ if (corner > end || corner < drv->corners) {
+ ret = -EINVAL;
+ goto unlock;
+ }
+
+ /* Determine direction */
+ if (drv->corner > corner)
+ dir = DOWN;
+ else if (drv->corner < corner)
+ dir = UP;
+ else
+ dir = NO_CHANGE;
+
+ if (cpr_is_allowed(drv))
+ new_uV = corner->last_uV;
+ else
+ new_uV = corner->uV;
+
+ if (cpr_is_allowed(drv))
+ cpr_ctl_disable(drv);
+
+ ret = cpr_scale_voltage(drv, corner, new_uV, dir);
+ if (ret)
+ goto unlock;
+
+ if (cpr_is_allowed(drv)) {
+ cpr_irq_clr(drv);
+ if (drv->corner != corner)
+ cpr_corner_restore(drv, corner);
+ cpr_ctl_enable(drv, corner);
+ }
+
+ drv->corner = corner;
+
+unlock:
+ mutex_unlock(&drv->lock);
+
+ return ret;
+}
+
+static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
+{
+ struct nvmem_cell *cell;
+ ssize_t len;
+ char *ret;
+ int i;
+
+ *data = 0;
+
+ cell = nvmem_cell_get(dev, cname);
+ if (IS_ERR(cell)) {
+ if (PTR_ERR(cell) != -EPROBE_DEFER)
+ dev_err(dev, "undefined cell %s\n", cname);
+ return PTR_ERR(cell);
+ }
+
+ ret = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+ if (IS_ERR(ret)) {
+ dev_err(dev, "can't read cell %s\n", cname);
+ return PTR_ERR(ret);
+ }
+
+ for (i = 0; i < len; i++)
+ *data |= ret[i] << (8 * i);
+
+ kfree(ret);
+ dev_dbg(dev, "efuse read(%s) = %x, bytes %zd\n", cname, *data, len);
+
+ return 0;
+}
+
+static int
+cpr_populate_ring_osc_idx(struct cpr_drv *drv)
+{
+ struct fuse_corner *fuse = drv->fuse_corners;
+ struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
+ const struct cpr_fuse *fuses = drv->cpr_fuses;
+ u32 data;
+ int ret;
+
+ for (; fuse < end; fuse++, fuses++) {
+ ret = cpr_read_efuse(drv->dev, fuses->ring_osc,
+ &data);
+ if (ret)
+ return ret;
+ fuse->ring_osc_idx = data;
+ }
+
+ return 0;
+}
+
+static int cpr_read_fuse_uV(const struct cpr_desc *desc,
+ const struct fuse_corner_data *fdata,
+ const char *init_v_efuse,
+ int step_volt,
+ struct cpr_drv *drv)
+{
+ int step_size_uV, steps, uV;
+ u32 bits = 0;
+ int ret;
+
+ ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits);
+ if (ret)
+ return ret;
+
+ steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
+ /* Not two's complement.. instead highest bit is sign bit */
+ if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
+ steps = -steps;
+
+ step_size_uV = desc->cpr_fuses.init_voltage_step;
+
+ uV = fdata->ref_uV + steps * step_size_uV;
+ return DIV_ROUND_UP(uV, step_volt) * step_volt;
+}
+
+static int cpr_fuse_corner_init(struct cpr_drv *drv)
+{
+ const struct cpr_desc *desc = drv->desc;
+ const struct cpr_fuse *fuses = drv->cpr_fuses;
+ const struct acc_desc *acc_desc = drv->acc_desc;
+ int i;
+ unsigned int step_volt;
+ struct fuse_corner_data *fdata;
+ struct fuse_corner *fuse, *end;
+ int uV;
+ const struct reg_sequence *accs;
+ int ret;
+
+ accs = acc_desc->settings;
+
+ step_volt = regulator_get_linear_step(drv->vdd_apc);
+ if (!step_volt)
+ return -EINVAL;
+
+ /* Populate fuse_corner members */
+ fuse = drv->fuse_corners;
+ end = &fuse[desc->num_fuse_corners - 1];
+ fdata = desc->cpr_fuses.fuse_corner_data;
+
+ for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
+ /*
+ * Update SoC voltages: platforms might choose a different
+ * regulators than the one used to characterize the algorithms
+ * (ie, init_voltage_step).
+ */
+ fdata->min_uV = roundup(fdata->min_uV, step_volt);
+ fdata->max_uV = roundup(fdata->max_uV, step_volt);
+
+ /* Populate uV */
+ uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
+ step_volt, drv);
+ if (uV < 0)
+ return uV;
+
+ fuse->min_uV = fdata->min_uV;
+ fuse->max_uV = fdata->max_uV;
+ fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
+
+ if (fuse == end) {
+ /*
+ * Allow the highest fuse corner's PVS voltage to
+ * define the ceiling voltage for that corner in order
+ * to support SoC's in which variable ceiling values
+ * are required.
+ */
+ end->max_uV = max(end->max_uV, end->uV);
+ }
+
+ /* Populate target quotient by scaling */
+ ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot);
+ if (ret)
+ return ret;
+
+ fuse->quot *= fdata->quot_scale;
+ fuse->quot += fdata->quot_offset;
+ fuse->quot += fdata->quot_adjust;
+ fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
+
+ /* Populate acc settings */
+ fuse->accs = accs;
+ fuse->num_accs = acc_desc->num_regs_per_fuse;
+ accs += acc_desc->num_regs_per_fuse;
+ }
+
+ /*
+ * Restrict all fuse corner PVS voltages based upon per corner
+ * ceiling and floor voltages.
+ */
+ for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
+ if (fuse->uV > fuse->max_uV)
+ fuse->uV = fuse->max_uV;
+ else if (fuse->uV < fuse->min_uV)
+ fuse->uV = fuse->min_uV;
+
+ ret = regulator_is_supported_voltage(drv->vdd_apc,
+ fuse->min_uV,
+ fuse->min_uV);
+ if (!ret) {
+ dev_err(drv->dev,
+ "min uV: %d (fuse corner: %d) not supported by regulator\n",
+ fuse->min_uV, i);
+ return -EINVAL;
+ }
+
+ ret = regulator_is_supported_voltage(drv->vdd_apc,
+ fuse->max_uV,
+ fuse->max_uV);
+ if (!ret) {
+ dev_err(drv->dev,
+ "max uV: %d (fuse corner: %d) not supported by regulator\n",
+ fuse->max_uV, i);
+ return -EINVAL;
+ }
+
+ dev_dbg(drv->dev,
+ "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n",
+ i, fuse->min_uV, fuse->uV, fuse->max_uV,
+ fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
+ }
+
+ return 0;
+}
+
+static int cpr_calculate_scaling(const char *quot_offset,
+ struct cpr_drv *drv,
+ const struct fuse_corner_data *fdata,
+ const struct corner *corner)
+{
+ u32 quot_diff = 0;
+ unsigned long freq_diff;
+ int scaling;
+ const struct fuse_corner *fuse, *prev_fuse;
+ int ret;
+
+ fuse = corner->fuse_corner;
+ prev_fuse = fuse - 1;
+
+ if (quot_offset) {
+ ret = cpr_read_efuse(drv->dev, quot_offset, "_diff);
+ if (ret)
+ return ret;
+
+ quot_diff *= fdata->quot_offset_scale;
+ quot_diff += fdata->quot_offset_adjust;
+ } else {
+ quot_diff = fuse->quot - prev_fuse->quot;
+ }
+
+ freq_diff = fuse->max_freq - prev_fuse->max_freq;
+ freq_diff /= 1000000; /* Convert to MHz */
+ scaling = 1000 * quot_diff / freq_diff;
+ return min(scaling, fdata->max_quot_scale);
+}
+
+static int cpr_interpolate(const struct corner *corner, int step_volt,
+ const struct fuse_corner_data *fdata)
+{
+ unsigned long f_high, f_low, f_diff;
+ int uV_high, uV_low, uV;
+ u64 temp, temp_limit;
+ const struct fuse_corner *fuse, *prev_fuse;
+
+ fuse = corner->fuse_corner;
+ prev_fuse = fuse - 1;
+
+ f_high = fuse->max_freq;
+ f_low = prev_fuse->max_freq;
+ uV_high = fuse->uV;
+ uV_low = prev_fuse->uV;
+ f_diff = fuse->max_freq - corner->freq;
+
+ /*
+ * Don't interpolate in the wrong direction. This could happen
+ * if the adjusted fuse voltage overlaps with the previous fuse's
+ * adjusted voltage.
+ */
+ if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
+ return corner->uV;
+
+ temp = f_diff * (uV_high - uV_low);
+ do_div(temp, f_high - f_low);
+
+ /*
+ * max_volt_scale has units of uV/MHz while freq values
+ * have units of Hz. Divide by 1000000 to convert to.
+ */
+ temp_limit = f_diff * fdata->max_volt_scale;
+ do_div(temp_limit, 1000000);
+
+ uV = uV_high - min(temp, temp_limit);
+ return roundup(uV, step_volt);
+}
+
+static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
+{
+ struct device_node *np;
+ unsigned int fuse_corner = 0;
+
+ np = dev_pm_opp_get_of_node(opp);
+ if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner))
+ pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
+ __func__);
+
+ of_node_put(np);
+
+ return fuse_corner;
+}
+
+static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref,
+ struct device *cpu_dev)
+{
+ u64 rate = 0;
+ struct device_node *ref_np;
+ struct device_node *desc_np;
+ struct device_node *child_np = NULL;
+ struct device_node *child_req_np = NULL;
+
+ desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
+ if (!desc_np)
+ return 0;
+
+ ref_np = dev_pm_opp_get_of_node(ref);
+ if (!ref_np)
+ goto out_ref;
+
+ do {
+ of_node_put(child_req_np);
+ child_np = of_get_next_available_child(desc_np, child_np);
+ child_req_np = of_parse_phandle(child_np, "required-opps", 0);
+ } while (child_np && child_req_np != ref_np);
+
+ if (child_np && child_req_np == ref_np)
+ of_property_read_u64(child_np, "opp-hz", &rate);
+
+ of_node_put(child_req_np);
+ of_node_put(child_np);
+ of_node_put(ref_np);
+out_ref:
+ of_node_put(desc_np);
+
+ return (unsigned long) rate;
+}
+
+static int cpr_corner_init(struct cpr_drv *drv)
+{
+ const struct cpr_desc *desc = drv->desc;
+ const struct cpr_fuse *fuses = drv->cpr_fuses;
+ int i, level, scaling = 0;
+ unsigned int fnum, fc;
+ const char *quot_offset;
+ struct fuse_corner *fuse, *prev_fuse;
+ struct corner *corner, *end;
+ struct corner_data *cdata;
+ const struct fuse_corner_data *fdata;
+ bool apply_scaling;
+ unsigned long freq_diff, freq_diff_mhz;
+ unsigned long freq;
+ int step_volt = regulator_get_linear_step(drv->vdd_apc);
+ struct dev_pm_opp *opp;
+
+ if (!step_volt)
+ return -EINVAL;
+
+ corner = drv->corners;
+ end = &corner[drv->num_corners - 1];
+
+ cdata = devm_kcalloc(drv->dev, drv->num_corners,
+ sizeof(struct corner_data),
+ GFP_KERNEL);
+ if (!cdata)
+ return -ENOMEM;
+
+ /*
+ * Store maximum frequency for each fuse corner based on the frequency
+ * plan
+ */
+ for (level = 1; level <= drv->num_corners; level++) {
+ opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level);
+ if (IS_ERR(opp))
+ return -EINVAL;
+ fc = cpr_get_fuse_corner(opp);
+ if (!fc) {
+ dev_pm_opp_put(opp);
+ return -EINVAL;
+ }
+ fnum = fc - 1;
+ freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev);
+ if (!freq) {
+ dev_pm_opp_put(opp);
+ return -EINVAL;
+ }
+ cdata[level - 1].fuse_corner = fnum;
+ cdata[level - 1].freq = freq;
+
+ fuse = &drv->fuse_corners[fnum];
+ dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
+ freq, dev_pm_opp_get_level(opp) - 1, fnum);
+ if (freq > fuse->max_freq)
+ fuse->max_freq = freq;
+ dev_pm_opp_put(opp);
+ }
+
+ /*
+ * Get the quotient adjustment scaling factor, according to:
+ *
+ * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
+ * / (freq(corner_N) - freq(corner_N-1)), max_factor)
+ *
+ * QUOT(corner_N): quotient read from fuse for fuse corner N
+ * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1)
+ * freq(corner_N): max frequency in MHz supported by fuse corner N
+ * freq(corner_N-1): max frequency in MHz supported by fuse corner
+ * (N - 1)
+ *
+ * Then walk through the corners mapped to each fuse corner
+ * and calculate the quotient adjustment for each one using the
+ * following formula:
+ *
+ * quot_adjust = (freq_max - freq_corner) * scaling / 1000
+ *
+ * freq_max: max frequency in MHz supported by the fuse corner
+ * freq_corner: frequency in MHz corresponding to the corner
+ * scaling: calculated from above equation
+ *
+ *
+ * + +
+ * | v |
+ * q | f c o | f c
+ * u | c l | c
+ * o | f t | f
+ * t | c a | c
+ * | c f g | c f
+ * | e |
+ * +--------------- +----------------
+ * 0 1 2 3 4 5 6 0 1 2 3 4 5 6
+ * corner corner
+ *
+ * c = corner
+ * f = fuse corner
+ *
+ */
+ for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
+ fnum = cdata[i].fuse_corner;
+ fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
+ quot_offset = fuses[fnum].quotient_offset;
+ fuse = &drv->fuse_corners[fnum];
+ if (fnum)
+ prev_fuse = &drv->fuse_corners[fnum - 1];
+ else
+ prev_fuse = NULL;
+
+ corner->fuse_corner = fuse;
+ corner->freq = cdata[i].freq;
+ corner->uV = fuse->uV;
+
+ if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
+ scaling = cpr_calculate_scaling(quot_offset, drv,
+ fdata, corner);
+ if (scaling < 0)
+ return scaling;
+
+ apply_scaling = true;
+ } else if (corner->freq == fuse->max_freq) {
+ /* This is a fuse corner; don't scale anything */
+ apply_scaling = false;
+ }
+
+ if (apply_scaling) {
+ freq_diff = fuse->max_freq - corner->freq;
+ freq_diff_mhz = freq_diff / 1000000;
+ corner->quot_adjust = scaling * freq_diff_mhz / 1000;
+
+ corner->uV = cpr_interpolate(corner, step_volt, fdata);
+ }
+
+ corner->max_uV = fuse->max_uV;
+ corner->min_uV = fuse->min_uV;
+ corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
+ corner->last_uV = corner->uV;
+
+ /* Reduce the ceiling voltage if needed */
+ if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
+ corner->max_uV = corner->uV;
+ else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
+ corner->max_uV = max(corner->min_uV, fuse->uV);
+
+ dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
+ corner->min_uV, corner->uV, corner->max_uV,
+ fuse->quot - corner->quot_adjust);
+ }
+
+ return 0;
+}
+
+static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
+{
+ const struct cpr_desc *desc = drv->desc;
+ struct cpr_fuse *fuses;
+ int i;
+
+ fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners,
+ sizeof(struct cpr_fuse),
+ GFP_KERNEL);
+ if (!fuses)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; i < desc->num_fuse_corners; i++) {
+ char tbuf[32];
+
+ snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
+ fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
+ if (!fuses[i].ring_osc)
+ return ERR_PTR(-ENOMEM);
+
+ snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
+ fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
+ GFP_KERNEL);
+ if (!fuses[i].init_voltage)
+ return ERR_PTR(-ENOMEM);
+
+ snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
+ fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
+ if (!fuses[i].quotient)
+ return ERR_PTR(-ENOMEM);
+
+ snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
+ fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
+ GFP_KERNEL);
+ if (!fuses[i].quotient_offset)
+ return ERR_PTR(-ENOMEM);
+ }
+
+ return fuses;
+}
+
+static void cpr_set_loop_allowed(struct cpr_drv *drv)
+{
+ drv->loop_disabled = false;
+}
+
+static int cpr_init_parameters(struct cpr_drv *drv)
+{
+ const struct cpr_desc *desc = drv->desc;
+ struct clk *clk;
+
+ clk = clk_get(drv->dev, "ref");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ drv->ref_clk_khz = clk_get_rate(clk) / 1000;
+ clk_put(clk);
+
+ if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK ||
+ desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK ||
+ desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK ||
+ desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK ||
+ desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK ||
+ desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK)
+ return -EINVAL;
+
+ dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
+ desc->up_threshold, desc->down_threshold);
+
+ return 0;
+}
+
+static int cpr_find_initial_corner(struct cpr_drv *drv)
+{
+ unsigned long rate;
+ const struct corner *end;
+ struct corner *iter;
+ unsigned int i = 0;
+
+ if (!drv->cpu_clk) {
+ dev_err(drv->dev, "cannot get rate from NULL clk\n");
+ return -EINVAL;
+ }
+
+ end = &drv->corners[drv->num_corners - 1];
+ rate = clk_get_rate(drv->cpu_clk);
+
+ /*
+ * Some bootloaders set a CPU clock frequency that is not defined
+ * in the OPP table. When running at an unlisted frequency,
+ * cpufreq_online() will change to the OPP which has the lowest
+ * frequency, at or above the unlisted frequency.
+ * Since cpufreq_online() always "rounds up" in the case of an
+ * unlisted frequency, this function always "rounds down" in case
+ * of an unlisted frequency. That way, when cpufreq_online()
+ * triggers the first ever call to cpr_set_performance_state(),
+ * it will correctly determine the direction as UP.
+ */
+ for (iter = drv->corners; iter <= end; iter++) {
+ if (iter->freq > rate)
+ break;
+ i++;
+ if (iter->freq == rate) {
+ drv->corner = iter;
+ break;
+ }
+ if (iter->freq < rate)
+ drv->corner = iter;
+ }
+
+ if (!drv->corner) {
+ dev_err(drv->dev, "boot up corner not found\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(drv->dev, "boot up perf state: %u\n", i);
+
+ return 0;
+}
+
+static const struct cpr_desc qcs404_cpr_desc = {
+ .num_fuse_corners = 3,
+ .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
+ .step_quot = (int []){ 25, 25, 25, },
+ .timer_delay_us = 5000,
+ .timer_cons_up = 0,
+ .timer_cons_down = 2,
+ .up_threshold = 1,
+ .down_threshold = 3,
+ .idle_clocks = 15,
+ .gcnt_us = 1,
+ .vdd_apc_step_up_limit = 1,
+ .vdd_apc_step_down_limit = 1,
+ .cpr_fuses = {
+ .init_voltage_step = 8000,
+ .init_voltage_width = 6,
+ .fuse_corner_data = (struct fuse_corner_data[]){
+ /* fuse corner 0 */
+ {
+ .ref_uV = 1224000,
+ .max_uV = 1224000,
+ .min_uV = 1048000,
+ .max_volt_scale = 0,
+ .max_quot_scale = 0,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 1 */
+ {
+ .ref_uV = 1288000,
+ .max_uV = 1288000,
+ .min_uV = 1048000,
+ .max_volt_scale = 2000,
+ .max_quot_scale = 1400,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = -20,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 2 */
+ {
+ .ref_uV = 1352000,
+ .max_uV = 1384000,
+ .min_uV = 1088000,
+ .max_volt_scale = 2000,
+ .max_quot_scale = 1400,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ },
+ },
+};
+
+static const struct acc_desc qcs404_acc_desc = {
+ .settings = (struct reg_sequence[]){
+ { 0xb120, 0x1041040 },
+ { 0xb124, 0x41 },
+ { 0xb120, 0x0 },
+ { 0xb124, 0x0 },
+ { 0xb120, 0x0 },
+ { 0xb124, 0x0 },
+ },
+ .config = (struct reg_sequence[]){
+ { 0xb138, 0xff },
+ { 0xb130, 0x5555 },
+ },
+ .num_regs_per_fuse = 2,
+};
+
+static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
+ .cpr_desc = &qcs404_cpr_desc,
+ .acc_desc = &qcs404_acc_desc,
+};
+
+static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
+static int cpr_power_off(struct generic_pm_domain *domain)
+{
+ struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+
+ return cpr_disable(drv);
+}
+
+static int cpr_power_on(struct generic_pm_domain *domain)
+{
+ struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+
+ return cpr_enable(drv);
+}
+
+static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
+ struct device *dev)
+{
+ struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+ const struct acc_desc *acc_desc = drv->acc_desc;
+ int ret = 0;
+
+ mutex_lock(&drv->lock);
+
+ dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
+
+ /*
+ * This driver only supports scaling voltage for a CPU cluster
+ * where all CPUs in the cluster share a single regulator.
+ * Therefore, save the struct device pointer only for the first
+ * CPU device that gets attached. There is no need to do any
+ * additional initialization when further CPUs get attached.
+ */
+ if (drv->attached_cpu_dev)
+ goto unlock;
+
+ /*
+ * cpr_scale_voltage() requires the direction (if we are changing
+ * to a higher or lower OPP). The first time
+ * cpr_set_performance_state() is called, there is no previous
+ * performance state defined. Therefore, we call
+ * cpr_find_initial_corner() that gets the CPU clock frequency
+ * set by the bootloader, so that we can determine the direction
+ * the first time cpr_set_performance_state() is called.
+ */
+ drv->cpu_clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(drv->cpu_clk)) {
+ ret = PTR_ERR(drv->cpu_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(drv->dev, "could not get cpu clk: %d\n", ret);
+ goto unlock;
+ }
+ drv->attached_cpu_dev = dev;
+
+ dev_dbg(drv->dev, "using cpu clk from: %s\n",
+ dev_name(drv->attached_cpu_dev));
+
+ /*
+ * Everything related to (virtual) corners has to be initialized
+ * here, when attaching to the power domain, since we need to know
+ * the maximum frequency for each fuse corner, and this is only
+ * available after the cpufreq driver has attached to us.
+ * The reason for this is that we need to know the highest
+ * frequency associated with each fuse corner.
+ */
+ ret = dev_pm_opp_get_opp_count(&drv->pd.dev);
+ if (ret < 0) {
+ dev_err(drv->dev, "could not get OPP count\n");
+ goto unlock;
+ }
+ drv->num_corners = ret;
+
+ if (drv->num_corners < 2) {
+ dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
+ ret = -EINVAL;
+ goto unlock;
+ }
+
+ drv->corners = devm_kcalloc(drv->dev, drv->num_corners,
+ sizeof(*drv->corners),
+ GFP_KERNEL);
+ if (!drv->corners) {
+ ret = -ENOMEM;
+ goto unlock;
+ }
+
+ ret = cpr_corner_init(drv);
+ if (ret)
+ goto unlock;
+
+ cpr_set_loop_allowed(drv);
+
+ ret = cpr_init_parameters(drv);
+ if (ret)
+ goto unlock;
+
+ /* Configure CPR HW but keep it disabled */
+ ret = cpr_config(drv);
+ if (ret)
+ goto unlock;
+
+ ret = cpr_find_initial_corner(drv);
+ if (ret)
+ goto unlock;
+
+ if (acc_desc->config)
+ regmap_multi_reg_write(drv->tcsr, acc_desc->config,
+ acc_desc->num_regs_per_fuse);
+
+ /* Enable ACC if required */
+ if (acc_desc->enable_mask)
+ regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
+ acc_desc->enable_mask,
+ acc_desc->enable_mask);
+
+ dev_info(drv->dev, "driver initialized with %u OPPs\n",
+ drv->num_corners);
+
+unlock:
+ mutex_unlock(&drv->lock);
+
+ return ret;
+}
+
+static int cpr_debug_info_show(struct seq_file *s, void *unused)
+{
+ u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
+ u32 step_dn, step_up, error, error_lt0, busy;
+ struct cpr_drv *drv = s->private;
+ struct fuse_corner *fuse_corner;
+ struct corner *corner;
+
+ corner = drv->corner;
+ fuse_corner = corner->fuse_corner;
+
+ seq_printf(s, "corner, current_volt = %d uV\n",
+ corner->last_uV);
+
+ ro_sel = fuse_corner->ring_osc_idx;
+ gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
+ seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt);
+
+ ctl = cpr_read(drv, REG_RBCPR_CTL);
+ seq_printf(s, "rbcpr_ctl = %#02X\n", ctl);
+
+ irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+ seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status);
+
+ reg = cpr_read(drv, REG_RBCPR_RESULT_0);
+ seq_printf(s, "rbcpr_result_0 = %#02X\n", reg);
+
+ step_dn = reg & 0x01;
+ step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
+ seq_printf(s, " [step_dn = %u", step_dn);
+
+ seq_printf(s, ", step_up = %u", step_up);
+
+ error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
+ & RBCPR_RESULT0_ERROR_STEPS_MASK;
+ seq_printf(s, ", error_steps = %u", error_steps);
+
+ error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
+ seq_printf(s, ", error = %u", error);
+
+ error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
+ seq_printf(s, ", error_lt_0 = %u", error_lt0);
+
+ busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
+ seq_printf(s, ", busy = %u]\n", busy);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(cpr_debug_info);
+
+static void cpr_debugfs_init(struct cpr_drv *drv)
+{
+ drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
+
+ debugfs_create_file("debug_info", 0444, drv->debugfs,
+ drv, &cpr_debug_info_fops);
+}
+
+static int cpr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct cpr_drv *drv;
+ int irq, ret;
+ const struct cpr_acc_desc *data;
+ struct device_node *np;
+ u32 cpr_rev = FUSE_REVISION_UNKNOWN;
+
+ data = of_device_get_match_data(dev);
+ if (!data || !data->cpr_desc || !data->acc_desc)
+ return -EINVAL;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+ drv->dev = dev;
+ drv->desc = data->cpr_desc;
+ drv->acc_desc = data->acc_desc;
+
+ drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
+ sizeof(*drv->fuse_corners),
+ GFP_KERNEL);
+ if (!drv->fuse_corners)
+ return -ENOMEM;
+
+ np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
+ if (!np)
+ return -ENODEV;
+
+ drv->tcsr = syscon_node_to_regmap(np);
+ of_node_put(np);
+ if (IS_ERR(drv->tcsr))
+ return PTR_ERR(drv->tcsr);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(drv->base))
+ return PTR_ERR(drv->base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return -EINVAL;
+
+ drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
+ if (IS_ERR(drv->vdd_apc))
+ return PTR_ERR(drv->vdd_apc);
+
+ /*
+ * Initialize fuse corners, since it simply depends
+ * on data in efuses.
+ * Everything related to (virtual) corners has to be
+ * initialized after attaching to the power domain,
+ * since it depends on the CPU's OPP table.
+ */
+ ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
+ if (ret)
+ return ret;
+
+ drv->cpr_fuses = cpr_get_fuses(drv);
+ if (IS_ERR(drv->cpr_fuses))
+ return PTR_ERR(drv->cpr_fuses);
+
+ ret = cpr_populate_ring_osc_idx(drv);
+ if (ret)
+ return ret;
+
+ ret = cpr_fuse_corner_init(drv);
+ if (ret)
+ return ret;
+
+ mutex_init(&drv->lock);
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ cpr_irq_handler,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ "cpr", drv);
+ if (ret)
+ return ret;
+
+ drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
+ GFP_KERNEL);
+ if (!drv->pd.name)
+ return -EINVAL;
+
+ drv->pd.power_off = cpr_power_off;
+ drv->pd.power_on = cpr_power_on;
+ drv->pd.set_performance_state = cpr_set_performance_state;
+ drv->pd.opp_to_performance_state = cpr_get_performance_state;
+ drv->pd.attach_dev = cpr_pd_attach_dev;
+
+ ret = pm_genpd_init(&drv->pd, NULL, true);
+ if (ret)
+ return ret;
+
+ ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, drv);
+ cpr_debugfs_init(drv);
+
+ return 0;
+}
+
+static int cpr_remove(struct platform_device *pdev)
+{
+ struct cpr_drv *drv = platform_get_drvdata(pdev);
+
+ if (cpr_is_allowed(drv)) {
+ cpr_ctl_disable(drv);
+ cpr_irq_set(drv, 0);
+ }
+
+ of_genpd_del_provider(pdev->dev.of_node);
+ pm_genpd_remove(&drv->pd);
+
+ debugfs_remove_recursive(drv->debugfs);
+
+ return 0;
+}
+
+static const struct of_device_id cpr_match_table[] = {
+ { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, cpr_match_table);
+
+static struct platform_driver cpr_driver = {
+ .probe = cpr_probe,
+ .remove = cpr_remove,
+ .driver = {
+ .name = "qcom-cpr",
+ .of_match_table = cpr_match_table,
+ },
+};
+module_platform_driver(cpr_driver);
+
+MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
+MODULE_LICENSE("GPL v2");
In a lot of cases there also need to be default settings initialized
to make some of them conform to expectations of the kernel.
+config ROCKCHIP_IODOMAIN
+ tristate "Rockchip IO domain support"
+ depends on OF
+ help
+ Say y here to enable support io domains on Rockchip SoCs. It is
+ necessary for the io domain setting of the SoC to match the
+ voltage supplied by the regulators.
+
config ROCKCHIP_PM_DOMAINS
bool "Rockchip generic power domain"
depends on PM
# Rockchip Soc drivers
#
obj-$(CONFIG_ROCKCHIP_GRF) += grf.o
+obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o
obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip IO Voltage Domain driver
+ *
+ * Copyright 2014 MundoReader S.L.
+ * Copyright 2014 Google, Inc.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define MAX_SUPPLIES 16
+
+/*
+ * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
+ * "Recommended Operating Conditions" for "Digital GPIO". When the typical
+ * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
+ *
+ * They are used like this:
+ * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
+ * SoC we're at 3.3.
+ * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
+ * that to be an error.
+ */
+#define MAX_VOLTAGE_1_8 1980000
+#define MAX_VOLTAGE_3_3 3600000
+
+#define PX30_IO_VSEL 0x180
+#define PX30_IO_VSEL_VCCIO6_SRC BIT(0)
+#define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
+
+#define RK3288_SOC_CON2 0x24c
+#define RK3288_SOC_CON2_FLASH0 BIT(7)
+#define RK3288_SOC_FLASH_SUPPLY_NUM 2
+
+#define RK3328_SOC_CON4 0x410
+#define RK3328_SOC_CON4_VCCIO2 BIT(7)
+#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
+
+#define RK3368_SOC_CON15 0x43c
+#define RK3368_SOC_CON15_FLASH0 BIT(14)
+#define RK3368_SOC_FLASH_SUPPLY_NUM 2
+
+#define RK3399_PMUGRF_CON0 0x180
+#define RK3399_PMUGRF_CON0_VSEL BIT(8)
+#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
+
+struct rockchip_iodomain;
+
+/**
+ * @supplies: voltage settings matching the register bits.
+ */
+struct rockchip_iodomain_soc_data {
+ int grf_offset;
+ const char *supply_names[MAX_SUPPLIES];
+ void (*init)(struct rockchip_iodomain *iod);
+};
+
+struct rockchip_iodomain_supply {
+ struct rockchip_iodomain *iod;
+ struct regulator *reg;
+ struct notifier_block nb;
+ int idx;
+};
+
+struct rockchip_iodomain {
+ struct device *dev;
+ struct regmap *grf;
+ const struct rockchip_iodomain_soc_data *soc_data;
+ struct rockchip_iodomain_supply supplies[MAX_SUPPLIES];
+};
+
+static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply,
+ int uV)
+{
+ struct rockchip_iodomain *iod = supply->iod;
+ u32 val;
+ int ret;
+
+ /* set value bit */
+ val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1;
+ val <<= supply->idx;
+
+ /* apply hiword-mask */
+ val |= (BIT(supply->idx) << 16);
+
+ ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val);
+ if (ret)
+ dev_err(iod->dev, "Couldn't write to GRF\n");
+
+ return ret;
+}
+
+static int rockchip_iodomain_notify(struct notifier_block *nb,
+ unsigned long event,
+ void *data)
+{
+ struct rockchip_iodomain_supply *supply =
+ container_of(nb, struct rockchip_iodomain_supply, nb);
+ int uV;
+ int ret;
+
+ /*
+ * According to Rockchip it's important to keep the SoC IO domain
+ * higher than (or equal to) the external voltage. That means we need
+ * to change it before external voltage changes happen in the case
+ * of an increase.
+ *
+ * Note that in the "pre" change we pick the max possible voltage that
+ * the regulator might end up at (the client requests a range and we
+ * don't know for certain the exact voltage). Right now we rely on the
+ * slop in MAX_VOLTAGE_1_8 and MAX_VOLTAGE_3_3 to save us if clients
+ * request something like a max of 3.6V when they really want 3.3V.
+ * We could attempt to come up with better rules if this fails.
+ */
+ if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
+ struct pre_voltage_change_data *pvc_data = data;
+
+ uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
+ } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
+ REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
+ uV = (unsigned long)data;
+ } else {
+ return NOTIFY_OK;
+ }
+
+ dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
+
+ if (uV > MAX_VOLTAGE_3_3) {
+ dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
+
+ if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
+ return NOTIFY_BAD;
+ }
+
+ ret = rockchip_iodomain_write(supply, uV);
+ if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
+ return NOTIFY_BAD;
+
+ dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
+ return NOTIFY_OK;
+}
+
+static void px30_iodomain_init(struct rockchip_iodomain *iod)
+{
+ int ret;
+ u32 val;
+
+ /* if no VCCIO6 supply we should leave things alone */
+ if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg)
+ return;
+
+ /*
+ * set vccio6 iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16);
+ ret = regmap_write(iod->grf, PX30_IO_VSEL, val);
+ if (ret < 0)
+ dev_warn(iod->dev, "couldn't update vccio6 ctrl\n");
+}
+
+static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
+{
+ int ret;
+ u32 val;
+
+ /* if no flash supply we should leave things alone */
+ if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg)
+ return;
+
+ /*
+ * set flash0 iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16);
+ ret = regmap_write(iod->grf, RK3288_SOC_CON2, val);
+ if (ret < 0)
+ dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
+}
+
+static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
+{
+ int ret;
+ u32 val;
+
+ /* if no vccio2 supply we should leave things alone */
+ if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg)
+ return;
+
+ /*
+ * set vccio2 iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
+ ret = regmap_write(iod->grf, RK3328_SOC_CON4, val);
+ if (ret < 0)
+ dev_warn(iod->dev, "couldn't update vccio2 vsel ctrl\n");
+}
+
+static void rk3368_iodomain_init(struct rockchip_iodomain *iod)
+{
+ int ret;
+ u32 val;
+
+ /* if no flash supply we should leave things alone */
+ if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg)
+ return;
+
+ /*
+ * set flash0 iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16);
+ ret = regmap_write(iod->grf, RK3368_SOC_CON15, val);
+ if (ret < 0)
+ dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
+}
+
+static void rk3399_pmu_iodomain_init(struct rockchip_iodomain *iod)
+{
+ int ret;
+ u32 val;
+
+ /* if no pmu io supply we should leave things alone */
+ if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg)
+ return;
+
+ /*
+ * set pmu io iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
+ ret = regmap_write(iod->grf, RK3399_PMUGRF_CON0, val);
+ if (ret < 0)
+ dev_warn(iod->dev, "couldn't update pmu io iodomain ctrl\n");
+}
+
+static const struct rockchip_iodomain_soc_data soc_data_px30 = {
+ .grf_offset = 0x180,
+ .supply_names = {
+ NULL,
+ "vccio6",
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ "vccio5",
+ "vccio-oscgpi",
+ },
+ .init = px30_iodomain_init,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
+ .grf_offset = 0x100,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "pmuio1",
+ "pmuio2",
+ },
+};
+
+/*
+ * On the rk3188 the io-domains are handled by a shared register with the
+ * lower 8 bits being still being continuing drive-strength settings.
+ */
+static const struct rockchip_iodomain_soc_data soc_data_rk3188 = {
+ .grf_offset = 0x104,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "ap0",
+ "ap1",
+ "cif",
+ "flash",
+ "vccio0",
+ "vccio1",
+ "lcdc0",
+ "lcdc1",
+ },
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3228 = {
+ .grf_offset = 0x418,
+ .supply_names = {
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ },
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
+ .grf_offset = 0x380,
+ .supply_names = {
+ "lcdc", /* LCDC_VDD */
+ "dvp", /* DVPIO_VDD */
+ "flash0", /* FLASH0_VDD (emmc) */
+ "flash1", /* FLASH1_VDD (sdio1) */
+ "wifi", /* APIO3_VDD (sdio0) */
+ "bb", /* APIO5_VDD */
+ "audio", /* APIO4_VDD */
+ "sdcard", /* SDMMC0_VDD (sdmmc) */
+ "gpio30", /* APIO1_VDD */
+ "gpio1830", /* APIO2_VDD */
+ },
+ .init = rk3288_iodomain_init,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
+ .grf_offset = 0x410,
+ .supply_names = {
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ "vccio5",
+ "vccio6",
+ "pmuio",
+ },
+ .init = rk3328_iodomain_init,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3368 = {
+ .grf_offset = 0x900,
+ .supply_names = {
+ NULL, /* reserved */
+ "dvp", /* DVPIO_VDD */
+ "flash0", /* FLASH0_VDD (emmc) */
+ "wifi", /* APIO2_VDD (sdio0) */
+ NULL,
+ "audio", /* APIO3_VDD */
+ "sdcard", /* SDMMC0_VDD (sdmmc) */
+ "gpio30", /* APIO1_VDD */
+ "gpio1830", /* APIO4_VDD (gpujtag) */
+ },
+ .init = rk3368_iodomain_init,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu = {
+ .grf_offset = 0x100,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "pmu", /*PMU IO domain*/
+ "vop", /*LCDC IO domain*/
+ },
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
+ .grf_offset = 0xe640,
+ .supply_names = {
+ "bt656", /* APIO2_VDD */
+ "audio", /* APIO5_VDD */
+ "sdmmc", /* SDMMC0_VDD */
+ "gpio1830", /* APIO4_VDD */
+ },
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = {
+ .grf_offset = 0x180,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "pmu1830", /* PMUIO2_VDD */
+ },
+ .init = rk3399_pmu_iodomain_init,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rv1108 = {
+ .grf_offset = 0x404,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio5",
+ "vccio6",
+ },
+
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
+ .grf_offset = 0x104,
+ .supply_names = {
+ "pmu",
+ },
+};
+
+static const struct of_device_id rockchip_iodomain_match[] = {
+ {
+ .compatible = "rockchip,px30-io-voltage-domain",
+ .data = (void *)&soc_data_px30
+ },
+ {
+ .compatible = "rockchip,px30-pmu-io-voltage-domain",
+ .data = (void *)&soc_data_px30_pmu
+ },
+ {
+ .compatible = "rockchip,rk3188-io-voltage-domain",
+ .data = &soc_data_rk3188
+ },
+ {
+ .compatible = "rockchip,rk3228-io-voltage-domain",
+ .data = &soc_data_rk3228
+ },
+ {
+ .compatible = "rockchip,rk3288-io-voltage-domain",
+ .data = &soc_data_rk3288
+ },
+ {
+ .compatible = "rockchip,rk3328-io-voltage-domain",
+ .data = &soc_data_rk3328
+ },
+ {
+ .compatible = "rockchip,rk3368-io-voltage-domain",
+ .data = &soc_data_rk3368
+ },
+ {
+ .compatible = "rockchip,rk3368-pmu-io-voltage-domain",
+ .data = &soc_data_rk3368_pmu
+ },
+ {
+ .compatible = "rockchip,rk3399-io-voltage-domain",
+ .data = &soc_data_rk3399
+ },
+ {
+ .compatible = "rockchip,rk3399-pmu-io-voltage-domain",
+ .data = &soc_data_rk3399_pmu
+ },
+ {
+ .compatible = "rockchip,rv1108-io-voltage-domain",
+ .data = &soc_data_rv1108
+ },
+ {
+ .compatible = "rockchip,rv1108-pmu-io-voltage-domain",
+ .data = &soc_data_rv1108_pmu
+ },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
+
+static int rockchip_iodomain_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ struct rockchip_iodomain *iod;
+ struct device *parent;
+ int i, ret = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ iod = devm_kzalloc(&pdev->dev, sizeof(*iod), GFP_KERNEL);
+ if (!iod)
+ return -ENOMEM;
+
+ iod->dev = &pdev->dev;
+ platform_set_drvdata(pdev, iod);
+
+ match = of_match_node(rockchip_iodomain_match, np);
+ iod->soc_data = match->data;
+
+ parent = pdev->dev.parent;
+ if (parent && parent->of_node) {
+ iod->grf = syscon_node_to_regmap(parent->of_node);
+ } else {
+ dev_dbg(&pdev->dev, "falling back to old binding\n");
+ iod->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ }
+
+ if (IS_ERR(iod->grf)) {
+ dev_err(&pdev->dev, "couldn't find grf regmap\n");
+ return PTR_ERR(iod->grf);
+ }
+
+ for (i = 0; i < MAX_SUPPLIES; i++) {
+ const char *supply_name = iod->soc_data->supply_names[i];
+ struct rockchip_iodomain_supply *supply = &iod->supplies[i];
+ struct regulator *reg;
+ int uV;
+
+ if (!supply_name)
+ continue;
+
+ reg = devm_regulator_get_optional(iod->dev, supply_name);
+ if (IS_ERR(reg)) {
+ ret = PTR_ERR(reg);
+
+ /* If a supply wasn't specified, that's OK */
+ if (ret == -ENODEV)
+ continue;
+ else if (ret != -EPROBE_DEFER)
+ dev_err(iod->dev, "couldn't get regulator %s\n",
+ supply_name);
+ goto unreg_notify;
+ }
+
+ /* set initial correct value */
+ uV = regulator_get_voltage(reg);
+
+ /* must be a regulator we can get the voltage of */
+ if (uV < 0) {
+ dev_err(iod->dev, "Can't determine voltage: %s\n",
+ supply_name);
+ goto unreg_notify;
+ }
+
+ if (uV > MAX_VOLTAGE_3_3) {
+ dev_crit(iod->dev,
+ "%d uV is too high. May damage SoC!\n",
+ uV);
+ ret = -EINVAL;
+ goto unreg_notify;
+ }
+
+ /* setup our supply */
+ supply->idx = i;
+ supply->iod = iod;
+ supply->reg = reg;
+ supply->nb.notifier_call = rockchip_iodomain_notify;
+
+ ret = rockchip_iodomain_write(supply, uV);
+ if (ret) {
+ supply->reg = NULL;
+ goto unreg_notify;
+ }
+
+ /* register regulator notifier */
+ ret = regulator_register_notifier(reg, &supply->nb);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "regulator notifier request failed\n");
+ supply->reg = NULL;
+ goto unreg_notify;
+ }
+ }
+
+ if (iod->soc_data->init)
+ iod->soc_data->init(iod);
+
+ return 0;
+
+unreg_notify:
+ for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
+ struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
+
+ if (io_supply->reg)
+ regulator_unregister_notifier(io_supply->reg,
+ &io_supply->nb);
+ }
+
+ return ret;
+}
+
+static int rockchip_iodomain_remove(struct platform_device *pdev)
+{
+ struct rockchip_iodomain *iod = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
+ struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
+
+ if (io_supply->reg)
+ regulator_unregister_notifier(io_supply->reg,
+ &io_supply->nb);
+ }
+
+ return 0;
+}
+
+static struct platform_driver rockchip_iodomain_driver = {
+ .probe = rockchip_iodomain_probe,
+ .remove = rockchip_iodomain_remove,
+ .driver = {
+ .name = "rockchip-iodomain",
+ .of_match_table = rockchip_iodomain_match,
+ },
+};
+
+module_platform_driver(rockchip_iodomain_driver);
+
+MODULE_DESCRIPTION("Rockchip IO-domain driver");
+MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
+MODULE_AUTHOR("Doug Anderson <dianders@chromium.org>");
+MODULE_LICENSE("GPL v2");
obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o
obj-$(CONFIG_TI_K3_RINGACC) += k3-ringacc.o
obj-$(CONFIG_TI_K3_SOCINFO) += k3-socinfo.o
+obj-$(CONFIG_POWER_AVS_OMAP) += smartreflex.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ */
+
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/power/smartreflex.h>
+
+#define DRIVER_NAME "smartreflex"
+#define SMARTREFLEX_NAME_LEN 32
+#define NVALUE_NAME_LEN 40
+#define SR_DISABLE_TIMEOUT 200
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct dentry *sr_dbg_dir;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+ __raw_writel(value, (sr->base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+ u32 value)
+{
+ u32 reg_val;
+
+ /*
+ * Smartreflex error config register is special as it contains
+ * certain status bits which if written a 1 into means a clear
+ * of those bits. So in order to make sure no accidental write of
+ * 1 happens to those status bits, do a clear of them in the read
+ * value. This mean this API doesn't rewrite values in these bits
+ * if they are currently set, but does allow the caller to write
+ * those bits.
+ */
+ if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
+ mask |= ERRCONFIG_STATUS_V1_MASK;
+ else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
+ mask |= ERRCONFIG_VPBOUNDINTST_V2;
+
+ reg_val = __raw_readl(sr->base + offset);
+ reg_val &= ~mask;
+
+ value &= mask;
+
+ reg_val |= value;
+
+ __raw_writel(reg_val, (sr->base + offset));
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+ return __raw_readl(sr->base + offset);
+}
+
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+ struct omap_sr *sr_info;
+
+ if (!voltdm) {
+ pr_err("%s: Null voltage domain passed!\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ list_for_each_entry(sr_info, &sr_list, node) {
+ if (voltdm == sr_info->voltdm)
+ return sr_info;
+ }
+
+ return ERR_PTR(-ENODATA);
+}
+
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+ struct omap_sr *sr_info = data;
+ u32 status = 0;
+
+ switch (sr_info->ip_type) {
+ case SR_TYPE_V1:
+ /* Read the status bits */
+ status = sr_read_reg(sr_info, ERRCONFIG_V1);
+
+ /* Clear them by writing back */
+ sr_write_reg(sr_info, ERRCONFIG_V1, status);
+ break;
+ case SR_TYPE_V2:
+ /* Read the status bits */
+ status = sr_read_reg(sr_info, IRQSTATUS);
+
+ /* Clear them by writing back */
+ sr_write_reg(sr_info, IRQSTATUS, status);
+ break;
+ default:
+ dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
+ sr_info->ip_type);
+ return IRQ_NONE;
+ }
+
+ if (sr_class->notify)
+ sr_class->notify(sr_info, status);
+
+ return IRQ_HANDLED;
+}
+
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+ struct clk *fck;
+ u32 fclk_speed;
+
+ /* Try interconnect target module fck first if it already exists */
+ fck = clk_get(sr->pdev->dev.parent, "fck");
+ if (IS_ERR(fck)) {
+ fck = clk_get(&sr->pdev->dev, "fck");
+ if (IS_ERR(fck)) {
+ dev_err(&sr->pdev->dev,
+ "%s: unable to get fck for device %s\n",
+ __func__, dev_name(&sr->pdev->dev));
+ return;
+ }
+ }
+
+ fclk_speed = clk_get_rate(fck);
+ clk_put(fck);
+
+ switch (fclk_speed) {
+ case 12000000:
+ sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+ break;
+ case 13000000:
+ sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+ break;
+ case 19200000:
+ sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+ break;
+ case 26000000:
+ sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+ break;
+ case 38400000:
+ sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "%s: Invalid fclk rate: %d\n",
+ __func__, fclk_speed);
+ break;
+ }
+}
+
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+ if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+ dev_warn(&sr->pdev->dev,
+ "%s: smartreflex class driver not registered\n",
+ __func__);
+ return;
+ }
+
+ if (!sr_class->enable(sr))
+ sr->autocomp_active = true;
+}
+
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+ if (!sr_class || !(sr_class->disable)) {
+ dev_warn(&sr->pdev->dev,
+ "%s: smartreflex class driver not registered\n",
+ __func__);
+ return;
+ }
+
+ if (sr->autocomp_active) {
+ sr_class->disable(sr, 1);
+ sr->autocomp_active = false;
+ }
+}
+
+/*
+ * This function handles the initializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currently this function registers interrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+ struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+ int ret = 0;
+
+ if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
+ ret = devm_request_irq(&sr_info->pdev->dev, sr_info->irq,
+ sr_interrupt, 0, sr_info->name, sr_info);
+ if (ret)
+ goto error;
+ disable_irq(sr_info->irq);
+ }
+
+ if (pdata && pdata->enable_on_init)
+ sr_start_vddautocomp(sr_info);
+
+ return ret;
+
+error:
+ list_del(&sr_info->node);
+ dev_err(&sr_info->pdev->dev, "%s: ERROR in registering interrupt handler. Smartreflex will not function as desired\n",
+ __func__);
+
+ return ret;
+}
+
+static void sr_v1_disable(struct omap_sr *sr)
+{
+ int timeout = 0;
+ int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+ ERRCONFIG_MCUBOUNDINTST;
+
+ /* Enable MCUDisableAcknowledge interrupt */
+ sr_modify_reg(sr, ERRCONFIG_V1,
+ ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+ /* Disable all other SR interrupts and clear the status as needed */
+ if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
+ errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
+ sr_modify_reg(sr, ERRCONFIG_V1,
+ (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+ ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+ errconf_val);
+
+ /*
+ * Wait for SR to be disabled.
+ * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+ */
+ sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+ ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+ timeout);
+
+ if (timeout >= SR_DISABLE_TIMEOUT)
+ dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+ __func__);
+
+ /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+ sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+ ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+ int timeout = 0;
+
+ /* Enable MCUDisableAcknowledge interrupt */
+ sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+ /*
+ * Disable all other SR interrupts and clear the status
+ * write to status register ONLY on need basis - only if status
+ * is set.
+ */
+ if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
+ sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+ ERRCONFIG_VPBOUNDINTST_V2);
+ else
+ sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+ 0x0);
+ sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+ IRQENABLE_MCUVALIDINT |
+ IRQENABLE_MCUBOUNDSINT));
+ sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+ IRQSTATUS_MCVALIDINT |
+ IRQSTATUS_MCBOUNDSINT));
+
+ /*
+ * Wait for SR to be disabled.
+ * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+ */
+ sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
+ IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+ timeout);
+
+ if (timeout >= SR_DISABLE_TIMEOUT)
+ dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+ __func__);
+
+ /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+ sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+ sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
+static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
+ struct omap_sr *sr, u32 efuse_offs)
+{
+ int i;
+
+ if (!sr->nvalue_table) {
+ dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+ __func__);
+ return NULL;
+ }
+
+ for (i = 0; i < sr->nvalue_count; i++) {
+ if (sr->nvalue_table[i].efuse_offs == efuse_offs)
+ return &sr->nvalue_table[i];
+ }
+
+ return NULL;
+}
+
+/* Public Functions */
+
+/**
+ * sr_configure_errgen() - Configures the SmartReflex to perform AVS using the
+ * error generator module.
+ * @sr: SR module to be configured.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct omap_sr *sr)
+{
+ u32 sr_config, sr_errconfig, errconfig_offs;
+ u32 vpboundint_en, vpboundint_st;
+ u32 senp_en = 0, senn_en = 0;
+ u8 senp_shift, senn_shift;
+
+ if (!sr) {
+ pr_warn("%s: NULL omap_sr from %pS\n",
+ __func__, (void *)_RET_IP_);
+ return -EINVAL;
+ }
+
+ if (!sr->clk_length)
+ sr_set_clk_length(sr);
+
+ senp_en = sr->senp_mod;
+ senn_en = sr->senn_mod;
+
+ sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ sr_config |= SRCONFIG_DELAYCTRL;
+ senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+ senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+ errconfig_offs = ERRCONFIG_V1;
+ vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+ vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+ break;
+ case SR_TYPE_V2:
+ senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+ senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+ errconfig_offs = ERRCONFIG_V2;
+ vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+ vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+ sr_write_reg(sr, SRCONFIG, sr_config);
+ sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+ (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+ (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT);
+ sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ sr_errconfig);
+
+ /* Enabling the interrupts if the ERROR module is used */
+ sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
+ vpboundint_en);
+
+ return 0;
+}
+
+/**
+ * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
+ * @sr: SR module to be configured.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable the error generator module inside the smartreflex module.
+ *
+ * Returns 0 on success and error value in case of failure.
+ */
+int sr_disable_errgen(struct omap_sr *sr)
+{
+ u32 errconfig_offs;
+ u32 vpboundint_en, vpboundint_st;
+
+ if (!sr) {
+ pr_warn("%s: NULL omap_sr from %pS\n",
+ __func__, (void *)_RET_IP_);
+ return -EINVAL;
+ }
+
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ errconfig_offs = ERRCONFIG_V1;
+ vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+ vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+ break;
+ case SR_TYPE_V2:
+ errconfig_offs = ERRCONFIG_V2;
+ vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+ vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Disable the Sensor and errorgen */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
+
+ /*
+ * Disable the interrupts of ERROR module
+ * NOTE: modify is a read, modify,write - an implicit OCP barrier
+ * which is required is present here - sequencing is critical
+ * at this point (after errgen is disabled, vpboundint disable)
+ */
+ sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
+ return 0;
+}
+
+/**
+ * sr_configure_minmax() - Configures the SmartReflex to perform AVS using the
+ * minmaxavg module.
+ * @sr: SR module to be configured.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct omap_sr *sr)
+{
+ u32 sr_config, sr_avgwt;
+ u32 senp_en = 0, senn_en = 0;
+ u8 senp_shift, senn_shift;
+
+ if (!sr) {
+ pr_warn("%s: NULL omap_sr from %pS\n",
+ __func__, (void *)_RET_IP_);
+ return -EINVAL;
+ }
+
+ if (!sr->clk_length)
+ sr_set_clk_length(sr);
+
+ senp_en = sr->senp_mod;
+ senn_en = sr->senn_mod;
+
+ sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE |
+ (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ sr_config |= SRCONFIG_DELAYCTRL;
+ senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+ senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+ break;
+ case SR_TYPE_V2:
+ senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+ senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+ sr_write_reg(sr, SRCONFIG, sr_config);
+ sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+ (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+ sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+
+ /*
+ * Enabling the interrupts if MINMAXAVG module is used.
+ * TODO: check if all the interrupts are mandatory
+ */
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ sr_modify_reg(sr, ERRCONFIG_V1,
+ (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+ ERRCONFIG_MCUBOUNDINTEN),
+ (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+ ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+ ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+ break;
+ case SR_TYPE_V2:
+ sr_write_reg(sr, IRQSTATUS,
+ IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+ IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+ sr_write_reg(sr, IRQENABLE_SET,
+ IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+ IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @sr: pointer to which the SR module to be configured belongs to.
+ * @volt: The voltage at which the Voltage domain associated with
+ * the smartreflex module is operating at.
+ * This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct omap_sr *sr, unsigned long volt)
+{
+ struct omap_volt_data *volt_data;
+ struct omap_sr_nvalue_table *nvalue_row;
+ int ret;
+
+ if (!sr) {
+ pr_warn("%s: NULL omap_sr from %pS\n",
+ __func__, (void *)_RET_IP_);
+ return -EINVAL;
+ }
+
+ volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
+
+ if (IS_ERR(volt_data)) {
+ dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table for nominal voltage %ld\n",
+ __func__, volt);
+ return PTR_ERR(volt_data);
+ }
+
+ nvalue_row = sr_retrieve_nvalue_row(sr, volt_data->sr_efuse_offs);
+
+ if (!nvalue_row) {
+ dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
+ __func__, volt);
+ return -ENODATA;
+ }
+
+ /* errminlimit is opp dependent and hence linked to voltage */
+ sr->err_minlimit = nvalue_row->errminlimit;
+
+ pm_runtime_get_sync(&sr->pdev->dev);
+
+ /* Check if SR is already enabled. If yes do nothing */
+ if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+ return 0;
+
+ /* Configure SR */
+ ret = sr_class->configure(sr);
+ if (ret)
+ return ret;
+
+ sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
+
+ /* SRCONFIG - enable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+ return 0;
+}
+
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @sr: pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct omap_sr *sr)
+{
+ if (!sr) {
+ pr_warn("%s: NULL omap_sr from %pS\n",
+ __func__, (void *)_RET_IP_);
+ return;
+ }
+
+ /* Check if SR clocks are already disabled. If yes do nothing */
+ if (pm_runtime_suspended(&sr->pdev->dev))
+ return;
+
+ /*
+ * Disable SR if only it is indeed enabled. Else just
+ * disable the clocks.
+ */
+ if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ sr_v1_disable(sr);
+ break;
+ case SR_TYPE_V2:
+ sr_v2_disable(sr);
+ break;
+ default:
+ dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
+ sr->ip_type);
+ }
+ }
+
+ pm_runtime_put_sync_suspend(&sr->pdev->dev);
+}
+
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data: The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+ struct omap_sr *sr_info;
+
+ if (!class_data) {
+ pr_warn("%s:, Smartreflex class data passed is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (sr_class) {
+ pr_warn("%s: Smartreflex class driver already registered\n",
+ __func__);
+ return -EBUSY;
+ }
+
+ sr_class = class_data;
+
+ /*
+ * Call into late init to do initializations that require
+ * both sr driver and sr class driver to be initiallized.
+ */
+ list_for_each_entry(sr_info, &sr_list, node)
+ sr_late_init(sr_info);
+
+ return 0;
+}
+
+/**
+ * omap_sr_enable() - API to enable SR clocks and to call into the
+ * registered smartreflex class enable API.
+ * @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+ struct omap_sr *sr = _sr_lookup(voltdm);
+
+ if (IS_ERR(sr)) {
+ pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
+ return;
+ }
+
+ if (!sr->autocomp_active)
+ return;
+
+ if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+ dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
+ __func__);
+ return;
+ }
+
+ sr_class->enable(sr);
+}
+
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ * processor voltage
+ * @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+ struct omap_sr *sr = _sr_lookup(voltdm);
+
+ if (IS_ERR(sr)) {
+ pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
+ return;
+ }
+
+ if (!sr->autocomp_active)
+ return;
+
+ if (!sr_class || !(sr_class->disable)) {
+ dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
+ __func__);
+ return;
+ }
+
+ sr_class->disable(sr, 0);
+}
+
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ * voltage processor voltage
+ * @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+ struct omap_sr *sr = _sr_lookup(voltdm);
+
+ if (IS_ERR(sr)) {
+ pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
+ return;
+ }
+
+ if (!sr->autocomp_active)
+ return;
+
+ if (!sr_class || !(sr_class->disable)) {
+ dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
+ __func__);
+ return;
+ }
+
+ sr_class->disable(sr, 1);
+}
+
+/* PM Debug FS entries to enable and disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+ struct omap_sr *sr_info = data;
+
+ if (!sr_info) {
+ pr_warn("%s: omap_sr struct not found\n", __func__);
+ return -EINVAL;
+ }
+
+ *val = sr_info->autocomp_active;
+
+ return 0;
+}
+
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+ struct omap_sr *sr_info = data;
+
+ if (!sr_info) {
+ pr_warn("%s: omap_sr struct not found\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Sanity check */
+ if (val > 1) {
+ pr_warn("%s: Invalid argument %lld\n", __func__, val);
+ return -EINVAL;
+ }
+
+ /* control enable/disable only if there is a delta in value */
+ if (sr_info->autocomp_active != val) {
+ if (!val)
+ sr_stop_vddautocomp(sr_info);
+ else
+ sr_start_vddautocomp(sr_info);
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+ omap_sr_autocomp_store, "%llu\n");
+
+static int omap_sr_probe(struct platform_device *pdev)
+{
+ struct omap_sr *sr_info;
+ struct omap_sr_data *pdata = pdev->dev.platform_data;
+ struct resource *mem, *irq;
+ struct dentry *nvalue_dir;
+ int i, ret = 0;
+
+ sr_info = devm_kzalloc(&pdev->dev, sizeof(struct omap_sr), GFP_KERNEL);
+ if (!sr_info)
+ return -ENOMEM;
+
+ sr_info->name = devm_kzalloc(&pdev->dev,
+ SMARTREFLEX_NAME_LEN, GFP_KERNEL);
+ if (!sr_info->name)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, sr_info);
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+ return -EINVAL;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ sr_info->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(sr_info->base)) {
+ dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+ return PTR_ERR(sr_info->base);
+ }
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_irq_safe(&pdev->dev);
+
+ snprintf(sr_info->name, SMARTREFLEX_NAME_LEN, "%s", pdata->name);
+
+ sr_info->pdev = pdev;
+ sr_info->srid = pdev->id;
+ sr_info->voltdm = pdata->voltdm;
+ sr_info->nvalue_table = pdata->nvalue_table;
+ sr_info->nvalue_count = pdata->nvalue_count;
+ sr_info->senn_mod = pdata->senn_mod;
+ sr_info->senp_mod = pdata->senp_mod;
+ sr_info->err_weight = pdata->err_weight;
+ sr_info->err_maxlimit = pdata->err_maxlimit;
+ sr_info->accum_data = pdata->accum_data;
+ sr_info->senn_avgweight = pdata->senn_avgweight;
+ sr_info->senp_avgweight = pdata->senp_avgweight;
+ sr_info->autocomp_active = false;
+ sr_info->ip_type = pdata->ip_type;
+
+ if (irq)
+ sr_info->irq = irq->start;
+
+ sr_set_clk_length(sr_info);
+
+ list_add(&sr_info->node, &sr_list);
+
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&pdev->dev);
+ goto err_list_del;
+ }
+
+ /*
+ * Call into late init to do initializations that require
+ * both sr driver and sr class driver to be initiallized.
+ */
+ if (sr_class) {
+ ret = sr_late_init(sr_info);
+ if (ret) {
+ pr_warn("%s: Error in SR late init\n", __func__);
+ goto err_list_del;
+ }
+ }
+
+ dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+ if (!sr_dbg_dir)
+ sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
+
+ sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
+
+ debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, sr_info->dbg_dir,
+ sr_info, &pm_sr_fops);
+ debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+ &sr_info->err_weight);
+ debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+ &sr_info->err_maxlimit);
+
+ nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+
+ if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
+ dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
+ __func__, sr_info->name);
+
+ ret = -ENODATA;
+ goto err_debugfs;
+ }
+
+ for (i = 0; i < sr_info->nvalue_count; i++) {
+ char name[NVALUE_NAME_LEN + 1];
+
+ snprintf(name, sizeof(name), "volt_%lu",
+ sr_info->nvalue_table[i].volt_nominal);
+ debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+ &(sr_info->nvalue_table[i].nvalue));
+ snprintf(name, sizeof(name), "errminlimit_%lu",
+ sr_info->nvalue_table[i].volt_nominal);
+ debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+ &(sr_info->nvalue_table[i].errminlimit));
+
+ }
+
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
+
+err_debugfs:
+ debugfs_remove_recursive(sr_info->dbg_dir);
+err_list_del:
+ list_del(&sr_info->node);
+
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
+}
+
+static int omap_sr_remove(struct platform_device *pdev)
+{
+ struct omap_sr_data *pdata = pdev->dev.platform_data;
+ struct omap_sr *sr_info;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+ return -EINVAL;
+ }
+
+ sr_info = _sr_lookup(pdata->voltdm);
+ if (IS_ERR(sr_info)) {
+ dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+ __func__);
+ return PTR_ERR(sr_info);
+ }
+
+ if (sr_info->autocomp_active)
+ sr_stop_vddautocomp(sr_info);
+ debugfs_remove_recursive(sr_info->dbg_dir);
+
+ pm_runtime_disable(&pdev->dev);
+ list_del(&sr_info->node);
+ return 0;
+}
+
+static void omap_sr_shutdown(struct platform_device *pdev)
+{
+ struct omap_sr_data *pdata = pdev->dev.platform_data;
+ struct omap_sr *sr_info;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+ return;
+ }
+
+ sr_info = _sr_lookup(pdata->voltdm);
+ if (IS_ERR(sr_info)) {
+ dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+ __func__);
+ return;
+ }
+
+ if (sr_info->autocomp_active)
+ sr_stop_vddautocomp(sr_info);
+
+ return;
+}
+
+static const struct of_device_id omap_sr_match[] = {
+ { .compatible = "ti,omap3-smartreflex-core", },
+ { .compatible = "ti,omap3-smartreflex-mpu-iva", },
+ { .compatible = "ti,omap4-smartreflex-core", },
+ { .compatible = "ti,omap4-smartreflex-mpu", },
+ { .compatible = "ti,omap4-smartreflex-iva", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, omap_sr_match);
+
+static struct platform_driver smartreflex_driver = {
+ .probe = omap_sr_probe,
+ .remove = omap_sr_remove,
+ .shutdown = omap_sr_shutdown,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = omap_sr_match,
+ },
+};
+
+static int __init sr_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&smartreflex_driver);
+ if (ret) {
+ pr_err("%s: platform driver register failed for SR\n",
+ __func__);
+ return ret;
+ }
+
+ return 0;
+}
+late_initcall(sr_init);
+
+static void __exit sr_exit(void)
+{
+ platform_driver_unregister(&smartreflex_driver);
+}
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
projects / linux-2.6-microblaze.git / commitdiff