drm/radeon: Correct Transmit Margin masks

Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.

Correct the mask to "7 << 7", which is the Transmit Margin field.

Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 62eab82..14cdfdf 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 05894d1..9b7042d 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);