drm/amdgpu: switch to common decode iv helper

The iv format is the same for all the soc15 adpater
and onwards and can share a common function to
decode iv.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 86072ab..a250e4f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -452,51 +452,6 @@ out:
        return (wptr & ih->ptr_mask);
 }
 
-/**
- * navi10_ih_decode_iv - decode an interrupt vector
- *
- * @adev: amdgpu_device pointer
- * @ih: IH ring buffer to decode
- * @entry: IV entry to place decoded information into
- *
- * Decodes the interrupt vector at the current rptr
- * position and also advance the position.
- */
-static void navi10_ih_decode_iv(struct amdgpu_device *adev,
-                               struct amdgpu_ih_ring *ih,
-                               struct amdgpu_iv_entry *entry)
-{
-       /* wptr/rptr are in bytes! */
-       u32 ring_index = ih->rptr >> 2;
-       uint32_t dw[8];
-
-       dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
-       dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
-       dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
-       dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
-       dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
-       dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
-       dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
-       dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
-
-       entry->client_id = dw[0] & 0xff;
-       entry->src_id = (dw[0] >> 8) & 0xff;
-       entry->ring_id = (dw[0] >> 16) & 0xff;
-       entry->vmid = (dw[0] >> 24) & 0xf;
-       entry->vmid_src = (dw[0] >> 31);
-       entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
-       entry->timestamp_src = dw[2] >> 31;
-       entry->pasid = dw[3] & 0xffff;
-       entry->pasid_src = dw[3] >> 31;
-       entry->src_data[0] = dw[4];
-       entry->src_data[1] = dw[5];
-       entry->src_data[2] = dw[6];
-       entry->src_data[3] = dw[7];
-
-       /* wptr/rptr are in bytes! */
-       ih->rptr += 32;
-}
-
 /**
  * navi10_ih_irq_rearm - rearm IRQ if lost
  *
@@ -793,7 +748,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
 
 static const struct amdgpu_ih_funcs navi10_ih_funcs = {
        .get_wptr = navi10_ih_get_wptr,
-       .decode_iv = navi10_ih_decode_iv,
+       .decode_iv = amdgpu_ih_decode_iv_helper,
        .set_rptr = navi10_ih_set_rptr
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 32c3dd0..6694df7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -378,51 +378,6 @@ out:
        return (wptr & ih->ptr_mask);
 }
 
-/**
- * vega10_ih_decode_iv - decode an interrupt vector
- *
- * @adev: amdgpu_device pointer
- * @ih: IH ring buffer to decode
- * @entry: IV entry to place decoded information into
- *
- * Decodes the interrupt vector at the current rptr
- * position and also advance the position.
- */
-static void vega10_ih_decode_iv(struct amdgpu_device *adev,
-                               struct amdgpu_ih_ring *ih,
-                               struct amdgpu_iv_entry *entry)
-{
-       /* wptr/rptr are in bytes! */
-       u32 ring_index = ih->rptr >> 2;
-       uint32_t dw[8];
-
-       dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
-       dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
-       dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
-       dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
-       dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
-       dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
-       dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
-       dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
-
-       entry->client_id = dw[0] & 0xff;
-       entry->src_id = (dw[0] >> 8) & 0xff;
-       entry->ring_id = (dw[0] >> 16) & 0xff;
-       entry->vmid = (dw[0] >> 24) & 0xf;
-       entry->vmid_src = (dw[0] >> 31);
-       entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
-       entry->timestamp_src = dw[2] >> 31;
-       entry->pasid = dw[3] & 0xffff;
-       entry->pasid_src = dw[3] >> 31;
-       entry->src_data[0] = dw[4];
-       entry->src_data[1] = dw[5];
-       entry->src_data[2] = dw[6];
-       entry->src_data[3] = dw[7];
-
-       /* wptr/rptr are in bytes! */
-       ih->rptr += 32;
-}
-
 /**
  * vega10_ih_irq_rearm - rearm IRQ if lost
  *
@@ -697,7 +652,7 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
 
 static const struct amdgpu_ih_funcs vega10_ih_funcs = {
        .get_wptr = vega10_ih_get_wptr,
-       .decode_iv = vega10_ih_decode_iv,
+       .decode_iv = amdgpu_ih_decode_iv_helper,
        .set_rptr = vega10_ih_set_rptr
 };