drm/rockchip: vop: Add output selection registers for RK312x

In contrast to RK3036, RK312x SoCs have multiple output channels such as
RGB (i.e. LVDS TTL), LVDS, DSI and HDMI.

In order to support that, this splits output from RK3036 and defines an
separate one for RK3126 with the registers required to enable the
appropriate output and setup the correct polarity.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231222174220.55249-3-knaerzche@gmail.com

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index c51ca82..b9ee020 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -227,11 +227,22 @@ static const struct vop_win_data rk3126_vop_win_data[] = {
          .type = DRM_PLANE_TYPE_CURSOR },
 };
 
+static const struct vop_output rk3126_output = {
+       .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
+       .hdmi_pin_pol = VOP_REG(RK3126_INT_SCALER, 0x7, 4),
+       .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
+       .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
+       .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
+       .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
+       .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28),
+       .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
+};
+
 static const struct vop_data rk3126_vop = {
        .intr = &rk3036_intr,
        .common = &rk3036_common,
        .modeset = &rk3036_modeset,
-       .output = &rk3036_output,
+       .output = &rk3126_output,
        .win = rk3126_vop_win_data,
        .win_size = ARRAY_SIZE(rk3126_vop_win_data),
        .max_output = { 1920, 1080 },

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 406e981..fbf1bcc 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -872,6 +872,9 @@
 /* rk3036 register definition end */
 
 /* rk3126 register definition */
+#define RK3126_INT_SCALER              0x0c
+
+/* win1 register */
 #define RK3126_WIN1_MST                        0x4c
 #define RK3126_WIN1_DSP_INFO           0x50
 #define RK3126_WIN1_DSP_ST             0x54