drm/i915/tgl: Program BW_BUDDY registers during display init

Gen12 can improve bandwidth efficiency by pairing up memory requests
with similar addresses.  We need to program the BW_BUDDY1 and BW_BUDDY2
registers according to the memory configuration during display
initialization to take advantage of this capability.

The magic numbers we program here feel like something that could
definitely change on future platforms, so let's use a table-based
programming scheme to make this easy to extend in the future.

v2:
 - Add separate table for Wa_1409767108.  (Stan)
 - Reorder structure reduce size by a word.  Page mask can still be up
   to 28 bits (even though current values are small) so we should keep
   it as a u32, but just using a u8 for DRAM type instead of the actual
   enum type saves space.  (Lucas, Ville)
 - Rename function to tgl_bw_buddy_init() to be more precise about what
   it does.  (Lucas)

Bspec: 49189
Bspec: 49218
Bspec: 52890
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205224848.76712-1-matthew.d.roper@intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce1b64f..0b3dd2a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4781,6 +4781,56 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_combo_phy_uninit(dev_priv);
 }
 
+struct buddy_page_mask {
+       u32 page_mask;
+       u8 type;
+       u8 num_channels;
+};
+
+static const struct buddy_page_mask tgl_buddy_page_masks[] = {
+       { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0xE },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0xF },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1F },
+       {}
+};
+
+static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
+       { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1 },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x3 },
+       {}
+};
+
+static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
+{
+       enum intel_dram_type type = dev_priv->dram_info.type;
+       u8 num_channels = dev_priv->dram_info.num_channels;
+       const struct buddy_page_mask *table;
+       int i;
+
+       if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+               /* Wa_1409767108: tgl */
+               table = wa_1409767108_buddy_page_masks;
+       else
+               table = tgl_buddy_page_masks;
+
+       for (i = 0; table[i].page_mask != 0; i++)
+               if (table[i].num_channels == num_channels &&
+                   table[i].type == type)
+                       break;
+
+       if (table[i].page_mask == 0) {
+               DRM_DEBUG_DRIVER("Unknown memory configuration; disabling address buddy logic.\n");
+               I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
+               I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+       } else {
+               I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
+               I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
+       }
+}
+
 static void icl_display_core_init(struct drm_i915_private *dev_priv,
                                  bool resume)
 {
@@ -4813,6 +4863,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
        /* 6. Setup MBUS. */
        icl_mbus_init(dev_priv);
 
+       /* 7. Program arbiter BW_BUDDY registers */
+       if (INTEL_GEN(dev_priv) >= 12)
+               tgl_bw_buddy_init(dev_priv);
+
        if (resume && dev_priv->csr.dmc_payload)
                intel_csr_load_program(dev_priv);
 }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a6376a..082190c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7765,6 +7765,14 @@ enum {
 #define GEN7_MSG_CTL   _MMIO(0x45010)
 #define  WAIT_FOR_PCH_RESET_ACK                (1 << 1)
 #define  WAIT_FOR_PCH_FLR_ACK          (1 << 0)
+
+#define BW_BUDDY1_CTL                  _MMIO(0x45140)
+#define BW_BUDDY2_CTL                  _MMIO(0x45150)
+#define   BW_BUDDY_DISABLE             REG_BIT(31)
+
+#define BW_BUDDY1_PAGE_MASK            _MMIO(0x45144)
+#define BW_BUDDY2_PAGE_MASK            _MMIO(0x45154)
+
 #define HSW_NDE_RSTWRN_OPT     _MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1 << 4)