ARM: dts: at91: use clock-controller name for sckc nodes
authorClaudiu Beznea <claudiu.beznea@microchip.com>
Wed, 17 May 2023 09:41:18 +0000 (12:41 +0300)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Mon, 22 May 2023 13:00:34 +0000 (16:00 +0300)
Use clock-controller generic name for slow clock controller nodes.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230517094119.2894220-5-claudiu.beznea@microchip.com
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9rl.dtsi
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/sam9x60.dtsi
arch/arm/boot/dts/sama5d2.dtsi
arch/arm/boot/dts/sama5d3.dtsi
arch/arm/boot/dts/sama5d4.dtsi

index 76afeb3..498cb92 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffd50 {
+                       clk32k: clock-controller@fffffd50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffd50 0x4>;
                                clocks = <&slow_xtal>;
index a12e6c4..d7e8a11 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffd50 {
+                       clk32k: clock-controller@fffffd50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffd50 0x4>;
                                clocks = <&slow_xtal>;
index af19ef2..0123ee4 100644 (file)
                                clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index 89aafb9..c8bedfa 100644 (file)
                                clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "microchip,sam9x60-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index 86009dd..5f632e3 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@f8048050 {
+                       clk32k: clock-controller@f8048050 {
                                compatible = "atmel,sama5d4-sckc";
                                reg = <0xf8048050 0x4>;
 
index 4524a16..0eebf6c 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "atmel,sama5d3-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index e94f3a6..de6c829 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fc068650 {
+                       clk32k: clock-controller@fc068650 {
                                compatible = "atmel,sama5d4-sckc";
                                reg = <0xfc068650 0x4>;
                                #clock-cells = <0>;