drm/amdgpu: Reduce redundant gpu resets on nbio v7.4

On nbio v7.4, ras controller interrupt and athub
interrupt are generated after injecting UE to PCIE,
but gpu reset only needs to be triggered once.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 8d80df9..a26a9be 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -414,8 +414,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
                /* ras_controller_int is dedicated for nbif ras error,
                 * not the global interrupt for sync flood
                 */
-               amdgpu_ras_set_fed(adev, true);
-               amdgpu_ras_reset_gpu(adev);
+               amdgpu_ras_global_ras_isr(adev);
        }
 
        amdgpu_ras_error_data_fini(&err_data);