drm/amd/display: Disable PG on NV12

[Why]
According to HW team, PG is dropped for NV12, but programming
the registers will still cause power to be consumed, so don't
program for NV12.

[How]
Set function pointer to NULL if NV12

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index af40ea5..53083e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1268,7 +1268,8 @@ void dcn10_init_hw(struct dc *dc)
                }
 
                //Enable ability to power gate / don't force power on permanently
-               hws->funcs.enable_power_gating_plane(hws, true);
+               if (hws->funcs.enable_power_gating_plane)
+                       hws->funcs.enable_power_gating_plane(hws, true);
 
                return;
        }
@@ -1385,8 +1386,8 @@ void dcn10_init_hw(struct dc *dc)
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }
-
-       hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+       if (hws->funcs.enable_power_gating_plane)
+               hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 
        if (dc->clk_mgr->funcs->notify_wm_ranges)
                dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 1061fac..080d458 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3760,6 +3760,15 @@ static bool dcn20_resource_construct(
 
        dcn20_hw_sequencer_construct(dc);
 
+       // IF NV12, set PG function pointer to NULL. It's not that
+       // PG isn't supported for NV12, it's that we don't want to
+       // program the registers because that will cause more power
+       // to be consumed. We could have created dcn20_init_hw to get
+       // the same effect by checking ASIC rev, but there was a
+       // request at some point to not check ASIC rev on hw sequencer.
+       if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
+               dc->hwseq->funcs.enable_power_gating_plane = NULL;
+
        dc->caps.max_planes =  pool->base.pipe_count;
 
        for (i = 0; i < dc->caps.max_planes; ++i)