drm/amd/display: fix dppclk rcg poweron check

[WHY & HOW]
dppclk rcg power down will flip the poweron flag in the cache to cause dppclk rcg will never
run the rcg ungate sequence in some condition. Wait 10us to let dpp dto fully ramp.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index e097d52..856615e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1187,6 +1187,7 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,
                /*we have this in hwss: disable_plane*/
                //dccg35_set_dppclk_rcg(dccg, dpp_inst, true);
        }
+       udelay(10);
        dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
 }
 
@@ -1676,7 +1677,7 @@ static void dccg35_dpp_root_clock_control(
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-       if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
+       if (dccg->dpp_clock_gated[dpp_inst] != clock_on)
                return;
 
        if (clock_on) {
@@ -1697,6 +1698,9 @@ static void dccg35_dpp_root_clock_control(
                //dccg35_set_dppclk_rcg(dccg, dpp_inst, true);
        }
 
+       // wait for clock to fully ramp
+       udelay(10);
+
        dccg->dpp_clock_gated[dpp_inst] = !clock_on;
        DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on);
 }