drm/amd/powerplay: add limit of pp_feature for smu (v3)
authorLikun Gao <Likun.Gao@amd.com>
Thu, 31 Jan 2019 06:11:04 +0000 (14:11 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 19 Mar 2019 20:04:02 +0000 (15:04 -0500)
Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.

v2: put pp_feature into struct amdgpu_pm.
v3: merge feature_mask with pp_feature.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

index c97649e..374e1d2 100644 (file)
@@ -703,7 +703,6 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
        void *pp_handle;
        const struct amd_pm_funcs *pp_funcs;
-       uint32_t pp_feature;
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
index 4f8fb4e..05cd5c4 100644 (file)
@@ -1506,7 +1506,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                        return -EAGAIN;
        }
 
-       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+       adev->pm.pp_feature = amdgpu_pp_feature_mask;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {
                if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
index 2fda77f..dca3540 100644 (file)
@@ -445,6 +445,9 @@ struct amdgpu_pm {
        uint32_t                smu_prv_buffer_size;
        struct amdgpu_bo        *smu_prv_buffer;
        bool ac_power;
+       /* powerplay feature */
+       uint32_t pp_feature;
+
 };
 
 #define R600_SSTU_DFLT                               0
index 97a60da..997932e 100644 (file)
@@ -390,7 +390,7 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev)
 
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 {
-       if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+       if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
                return;
 
        if (!adev->powerplay.pp_funcs || !adev->powerplay.pp_funcs->set_powergating_by_smu)
index e05108e..8836201 100644 (file)
@@ -2569,7 +2569,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                "pp_power_profile_mode\n");
                return ret;
        }
-       if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
+       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+           (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
                ret = device_create_file(adev->dev,
                                &dev_attr_pp_od_clk_voltage);
                if (ret) {
@@ -2645,7 +2646,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
        device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
        device_remove_file(adev->dev,
                        &dev_attr_pp_power_profile_mode);
-       if (hwmgr->od_enabled)
+       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+           (!is_support_sw_smu(adev) && hwmgr->od_enabled))
                device_remove_file(adev->dev,
                                &dev_attr_pp_od_clk_voltage);
        device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
index 0c9a2c0..f2e6b14 100644 (file)
@@ -2824,7 +2824,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
                pi->caps_tcp_ramping = true;
        }
 
-       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+       if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;
index 9f6ce6e..e172114 100644 (file)
@@ -933,7 +933,7 @@ static int soc15_common_early_init(void *handle)
                        adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
                }
 
-               if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+               if (adev->pm.pp_feature & PP_GFXOFF_MASK)
                        adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
                                AMD_PG_SUPPORT_CP |
                                AMD_PG_SUPPORT_RLC_SMU_HS;
index 3f73f7c..a66917d 100644 (file)
@@ -53,7 +53,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
        mutex_init(&hwmgr->smu_lock);
        hwmgr->chip_family = adev->family;
        hwmgr->chip_id = adev->asic_type;
-       hwmgr->feature_mask = adev->powerplay.pp_feature;
+       hwmgr->feature_mask = adev->pm.pp_feature;
        hwmgr->display_config = &adev->pm.pm_display_cfg;
        adev->powerplay.pp_handle = hwmgr;
        adev->powerplay.pp_funcs = &pp_dpm_funcs;
index fa6248d..fe2f7e2 100644 (file)
@@ -291,6 +291,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+               adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+               if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+                       smu->od_enabled = true;
                smu_v11_0_set_smu_funcs(smu);
                break;
        default:
index 8fdad32..3e79fd9 100644 (file)
@@ -384,6 +384,7 @@ struct smu_context
        uint32_t pstate_sclk;
        uint32_t pstate_mclk;
 
+       bool od_enabled;
        uint32_t power_limit;
        uint32_t default_power_limit;