drm/amdgpu: Use 5-level paging if gmc support 57-bit VA

Regardless if CPU enable 5-level paging, GPU vm use 5-level paging if
gmc init with 57-bit address space support, because

ARM64 4-level paging support 48-bit VA, x86 and GPU 4-level paging
support 47-bit VA, require 5-level paging on GPU to support ARM64.

NPA address space 52-bit mapping on NPA GPU VM require 5-level paging.

Debugger trap get device snapshot expect LDS and Scratch base, limit
above 57-bit, which is set only for 5-level paging.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.19.x

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6a2ea20..3138358 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2360,26 +2360,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
                           unsigned max_bits)
 {
        unsigned int max_size = 1 << (max_bits - 30);
-       bool sys_5level_pgtable = false;
        unsigned int vm_size;
        uint64_t tmp;
 
-#ifdef CONFIG_X86_64
-       /*
-        * Refer to function configure_5level_paging() for details.
-        */
-       sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57);
-#endif
-
-       /*
-        * If GPU supports 5-level page table, but system uses 4-level page table,
-        * then use 4-level page table on GPU
-        */
-       if (max_level == 4 && !sys_5level_pgtable) {
-               min_vm_size = 256 * 1024;
-               max_level = 3;
-       }
-
        /* adjust vm size first */
        if (amdgpu_vm_size != -1) {
                vm_size = amdgpu_vm_size;