net: hns3: rename process_hw_error function
authorShiju Jose <shiju.jose@huawei.com>
Fri, 7 Dec 2018 21:08:02 +0000 (21:08 +0000)
committerDavid S. Miller <davem@davemloft.net>
Fri, 7 Dec 2018 23:57:01 +0000 (15:57 -0800)
This patch renames process_hw_error function to
handle_hw_ras_error function to match the purpose
of the function. This is because hw errors reported through
ras and msix interrupts will be handled separately.

Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hnae3.h
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

index a1707b7..9d9f4f9 100644 (file)
@@ -454,7 +454,7 @@ struct hnae3_ae_ops {
        int (*restore_fd_rules)(struct hnae3_handle *handle);
        void (*enable_fd)(struct hnae3_handle *handle, bool enable);
        int (*dbg_run_cmd)(struct hnae3_handle *handle, char *cmd_buf);
-       pci_ers_result_t (*process_hw_error)(struct hnae3_ae_dev *ae_dev);
+       pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
        bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
        bool (*ae_dev_resetting)(struct hnae3_handle *handle);
        unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
index d1b2de2..69142a3 100644 (file)
@@ -1828,8 +1828,8 @@ static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
                return PCI_ERS_RESULT_NONE;
        }
 
-       if (ae_dev->ops->process_hw_error)
-               ret = ae_dev->ops->process_hw_error(ae_dev);
+       if (ae_dev->ops->handle_hw_ras_error)
+               ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
        else
                return PCI_ERS_RESULT_NONE;
 
index 62fab23..2d07be8 100644 (file)
@@ -603,7 +603,7 @@ int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state)
        return ret;
 }
 
-pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev)
+pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
 {
        struct hclge_dev *hdev = ae_dev->priv;
        struct device *dev = &hdev->pdev->dev;
index 405739b..9fe1c96 100644 (file)
@@ -59,5 +59,5 @@ struct hclge_hw_error {
 };
 
 int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
-pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
+pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
 #endif
index 431d92a..354ac5f 100644 (file)
@@ -7935,7 +7935,7 @@ static const struct hnae3_ae_ops hclge_ops = {
        .restore_fd_rules = hclge_restore_fd_entries,
        .enable_fd = hclge_enable_fd,
        .dbg_run_cmd = hclge_dbg_run_cmd,
-       .process_hw_error = hclge_process_ras_hw_error,
+       .handle_hw_ras_error = hclge_handle_hw_ras_error,
        .get_hw_reset_stat = hclge_get_hw_reset_stat,
        .ae_dev_resetting = hclge_ae_dev_resetting,
        .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,