clk: qcom: dispcc-sdm845: get rid of the test clock

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-16-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index aef1024..735adfe 100644 (file)
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -21,7 +21,6 @@
 
 enum {
        P_BI_TCXO,
-       P_CORE_BI_PLL_TEST_SE,
        P_DISP_CC_PLL0_OUT_MAIN,
        P_DSI0_PHY_PLL_OUT_BYTECLK,
        P_DSI0_PHY_PLL_OUT_DSICLK,
@@ -52,38 +51,32 @@ static const struct parent_map disp_cc_parent_map_0[] = {
        { P_BI_TCXO, 0 },
        { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
        { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
-       { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data disp_cc_parent_data_0[] = {
        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
        { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
        { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
-       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map disp_cc_parent_map_1[] = {
        { P_BI_TCXO, 0 },
        { P_DP_PHY_PLL_LINK_CLK, 1 },
        { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
-       { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data disp_cc_parent_data_1[] = {
        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
        { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
        { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
-       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map disp_cc_parent_map_2[] = {
        { P_BI_TCXO, 0 },
-       { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data disp_cc_parent_data_2[] = {
        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
-       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map disp_cc_parent_map_3[] = {
@@ -91,7 +84,6 @@ static const struct parent_map disp_cc_parent_map_3[] = {
        { P_DISP_CC_PLL0_OUT_MAIN, 1 },
        { P_GPLL0_OUT_MAIN, 4 },
        { P_GPLL0_OUT_MAIN_DIV, 5 },
-       { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data disp_cc_parent_data_3[] = {
@@ -99,21 +91,18 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
        { .hw = &disp_cc_pll0.clkr.hw },
        { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
        { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
-       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map disp_cc_parent_map_4[] = {
        { P_BI_TCXO, 0 },
        { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
        { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
-       { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data disp_cc_parent_data_4[] = {
        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
        { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
        { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
-       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 /* Return the HW recalc rate for idle use case */