clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent

Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c
index 2410822..ec5b44f 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8192-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8192-mfg.c
@@ -18,8 +18,10 @@ static const struct mtk_gate_regs mfg_cg_regs = {
        .sta_ofs = 0x0,
 };
 
-#define GATE_MFG(_id, _name, _parent, _shift)  \
-       GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+#define GATE_MFG(_id, _name, _parent, _shift)                  \
+       GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs,       \
+                      _shift, &mtk_clk_gate_ops_setclr,        \
+                      CLK_SET_RATE_PARENT)
 
 static const struct mtk_gate mfg_clks[] = {
        GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),