Merge tag 'mvebu-dt64-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclemen...
authorArnd Bergmann <arnd@arndb.de>
Fri, 24 Jul 2020 14:07:45 +0000 (16:07 +0200)
committerArnd Bergmann <arnd@arndb.de>
Fri, 24 Jul 2020 14:07:45 +0000 (16:07 +0200)
mvebu dt64 for 5.9 (part 1)

Add SMMU support for the Marvell AP806 based SoCs (Armada 70xx and
Armada 80xx)

* tag 'mvebu-dt64-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: add SMMU support

arch/arm64/boot/dts/marvell/armada-7040.dtsi
arch/arm64/boot/dts/marvell/armada-8040.dtsi
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi

index 4724721..7a3198c 100644 (file)
        compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
                     "marvell,armada-ap806";
 };
+
+&smmu {
+       status = "okay";
+};
+
+&cp0_pcie0 {
+       iommu-map =
+               <0x0   &smmu 0x480 0x20>,
+               <0x100 &smmu 0x4a0 0x20>,
+               <0x200 &smmu 0x4c0 0x20>;
+       iommu-map-mask = <0x031f>;
+};
+
+&cp0_sata0 {
+       iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+       iommus = <&smmu 0x445>;
+};
+
+&cp0_usb3_0 {
+       iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+       iommus = <&smmu 0x441>;
+};
index 7699b19..79e8ce5 100644 (file)
                     "marvell,armada-ap806";
 };
 
+&smmu {
+       status = "okay";
+};
+
+&cp0_pcie0 {
+       iommu-map =
+               <0x0   &smmu 0x480 0x20>,
+               <0x100 &smmu 0x4a0 0x20>,
+               <0x200 &smmu 0x4c0 0x20>;
+       iommu-map-mask = <0x031f>;
+};
+
 /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
  * in CP master is not connected (by package) to the oscillator. So
  * disable it. However, the RTC clock in CP slave is connected to the
 &cp0_rtc {
        status = "disabled";
 };
+
+&cp0_sata0 {
+       iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+       iommus = <&smmu 0x445>;
+};
+
+&cp0_usb3_0 {
+       iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+       iommus = <&smmu 0x441>;
+};
+
+&cp1_sata0 {
+       iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+       iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+       iommus = <&smmu 0x451>;
+};
index 7f9b9a6..12e477f 100644 (file)
                        compatible = "simple-bus";
                        ranges = <0x0 0x0 0xf0000000 0x1000000>;
 
+                       smmu: iommu@5000000 {
+                               compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+                               reg = <0x100000 0x100000>;
+                               dma-coherent;
+                               #iommu-cells = <1>;
+                               #global-interrupts = <1>;
+                               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
+                       };
+
                        gic: interrupt-controller@210000 {
                                compatible = "arm,gic-400";
                                #interrupt-cells = <3>;