arm64: dts: renesas: beacon-rzg2m-kit: Rearrange SoC unique functions
authorAdam Ford <aford173@gmail.com>
Thu, 24 Dec 2020 17:04:59 +0000 (11:04 -0600)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 11 Jan 2021 09:01:29 +0000 (10:01 +0100)
In preparation for adding new dev kits, move anything specific to the
RZ/G2M from the SOM-level and baseboard-levels and move them to the
kit-level.  This allows the SOM and baseboard to be reused with
other SoC's.

Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201224170502.2254683-6-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts

index ae0f58e..30c169b 100644 (file)
        status = "okay";
 };
 
-&du {
-       pinctrl-0 = <&du_pins>;
-       pinctrl-names = "default";
-       status = "okay";
-
-       clocks = <&cpg CPG_MOD 724>,
-               <&cpg CPG_MOD 723>,
-               <&cpg CPG_MOD 722>,
-               <&versaclock5 1>,
-               <&x302_clk>,
-               <&versaclock5 2>;
-       clock-names = "du.0", "du.1", "du.2",
-               "dclkin.0", "dclkin.1", "dclkin.2";
-};
-
 &du_out_rgb {
        remote-endpoint = <&rgb_panel>;
 };
index 6e74c39..f4201e1 100644 (file)
                reg = <0x0 0x48000000 0x0 0x78000000>;
        };
 
-       memory@600000000 {
-               device_type = "memory";
-               reg = <0x6 0x00000000 0x0 0x80000000>;
-       };
-
        osc_32k: osc_32k {
                compatible = "fixed-clock";
                #clock-cells = <0>;
index 25eeac4..501cb05 100644 (file)
        chosen {
                stdout-path = "serial0:115200n8";
        };
+
+       memory@600000000 {
+               device_type = "memory";
+               reg = <0x6 0x00000000 0x0 0x80000000>;
+       };
+};
+
+&du {
+       pinctrl-0 = <&du_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 724>,
+                <&cpg CPG_MOD 723>,
+                <&cpg CPG_MOD 722>,
+                <&versaclock5 1>,
+                <&x302_clk>,
+                <&versaclock5 2>;
+       clock-names = "du.0", "du.1", "du.2",
+                     "dclkin.0", "dclkin.1", "dclkin.2";
 };
 
 /* Reference versaclock instead of audio_clk_a */