Merge tag 'x86-cpu-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cpu updates from Ingo Molar:

 - prepare for Intel's new SERIALIZE instruction

 - enable split-lock debugging on more CPUs

 - add more Intel CPU models

 - optimize stack canary initialization a bit

 - simplify the Spectre logic a bit

* tag 'x86-cpu-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Refactor sync_core() for readability
  x86/cpu: Relocate sync_core() to sync_core.h
  x86/cpufeatures: Add enumeration for SERIALIZE instruction
  x86/split_lock: Enable the split lock feature on Sapphire Rapids and Alder Lake CPUs
  x86/cpu: Add Lakefield, Alder Lake and Rocket Lake models to the to Intel CPU family
  x86/stackprotector: Pre-initialize canary for secondary CPUs
  x86/speculation: Merge one test in spectre_v2_user_select_mitigation()

diff --cc arch/x86/include/asm/cpufeatures.h
index 03390a1,adf45cf..2901d5d
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -367,8 -365,8 +367,9 @@@
  #define X86_FEATURE_SRBDS_CTRL                (18*32+ 9) /* "" SRBDS mitigation MSR available */
  #define X86_FEATURE_MD_CLEAR          (18*32+10) /* VERW clears CPU buffers */
  #define X86_FEATURE_TSX_FORCE_ABORT   (18*32+13) /* "" TSX_FORCE_ABORT */
+ #define X86_FEATURE_SERIALIZE         (18*32+14) /* SERIALIZE instruction */
  #define X86_FEATURE_PCONFIG           (18*32+18) /* Intel PCONFIG */
 +#define X86_FEATURE_ARCH_LBR          (18*32+19) /* Intel ARCH LBR */
  #define X86_FEATURE_SPEC_CTRL         (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
  #define X86_FEATURE_INTEL_STIBP               (18*32+27) /* "" Single Thread Indirect Branch Predictors */
  #define X86_FEATURE_FLUSH_L1D         (18*32+28) /* Flush L1D cache */

diff --cc arch/x86/kernel/alternative.c
Simple merge

diff --cc arch/x86/kernel/smpboot.c
Simple merge