ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
if (ret)
return ret;
- ret = dma_set_max_seg_size(&pdev->dev, UINT_MAX);
- if (ret)
- return ret;
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
qdev->bar_0 = devm_ioremap_resource(&pdev->dev, &pdev->resource[0]);
if (IS_ERR(qdev->bar_0))
idma64->dma.dev = chip->sysdev;
- ret = dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
- if (ret)
- return ret;
+ dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
ret = dma_async_device_register(&idma64->dma);
if (ret)
* This is the limit for transfers with a buswidth of 1, larger
* buswidths will have larger limits.
*/
- ret = dma_set_max_seg_size(&adev->dev, 1900800);
- if (ret)
- dev_err(&adev->dev, "unable to set the seg size\n");
-
+ dma_set_max_seg_size(&adev->dev, 1900800);
init_pl330_debugfs(pl330);
dev_info(&adev->dev,
/* set max dma segment size */
bdev->common.dev = bdev->dev;
- ret = dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
- if (ret) {
- dev_err(bdev->dev, "cannot set maximum segment size\n");
- goto err_bam_channel_exit;
- }
+ dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
platform_set_drvdata(pdev, bdev);
dmac->dev = &pdev->dev;
platform_set_drvdata(pdev, dmac);
- ret = dma_set_max_seg_size(dmac->dev, RCAR_DMATCR_MASK);
- if (ret)
- return ret;
+ dma_set_max_seg_size(dmac->dev, RCAR_DMATCR_MASK);
ret = dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40));
if (ret)
if (ret)
goto destroy_cache;
- ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
- if (ret) {
- d40_err(dev, "Failed to set dma max seg size\n");
- goto destroy_cache;
- }
+ dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
d40_hw_init(base);
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
- ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
- if (ret) {
- dev_err(dma_dev, "Failed to set DMA segment size\n");
- goto err_component_unbind;
- }
+ dma_set_max_seg_size(dma_dev, UINT_MAX);
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret < 0)
return -ENODEV;
}
if (dma_get_max_seg_size(dev) < size)
- return dma_set_max_seg_size(dev, size);
-
+ dma_set_max_seg_size(dev, size);
return 0;
}
EXPORT_SYMBOL_GPL(vb2_dma_contig_set_max_seg_size);
if (ret)
return dev_err_probe(dev, ret, "Failed to set DMA mask\n");
- ret = dma_set_max_seg_size(dev, UINT_MAX);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to set max_seg_size\n");
+ dma_set_max_seg_size(dev, UINT_MAX);
ret = ipu6_pci_config_setup(pdev, isp->hw_ver);
if (ret)
host->mmc->max_seg_size = host->mmc->max_req_size;
}
- return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
+ dma_set_max_seg_size(dev, host->mmc->max_seg_size);
+ return 0;
}
static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
if (err)
goto release_region;
- err = dma_set_max_seg_size(&pdev->dev, UINT_MAX);
- if (err) {
- dev_err(&pdev->dev, "Failed to set dma device segment size\n");
- goto release_region;
- }
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
err = -ENOMEM;
gc = vzalloc(sizeof(*gc));
if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
- rc = dma_set_max_seg_size(&phba->pcidev->dev, sli4_params->sge_supp_len);
- if (unlikely(rc)) {
- lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
- "6400 Can't set dma maximum segment size\n");
- return rc;
- }
+ dma_set_max_seg_size(&phba->pcidev->dev, sli4_params->sge_supp_len);
/*
* Check whether the adapter supports an embedded copy of the
return SZ_64K;
}
-static inline int dma_set_max_seg_size(struct device *dev, unsigned int size)
+static inline void dma_set_max_seg_size(struct device *dev, unsigned int size)
{
- if (dev->dma_parms) {
- dev->dma_parms->max_segment_size = size;
- return 0;
- }
- return -EIO;
+ if (WARN_ON_ONCE(!dev->dma_parms))
+ return;
+ dev->dma_parms->max_segment_size = size;
}
static inline unsigned long dma_get_seg_boundary(struct device *dev)