{
u8 center_ch = channel;
- if (chnl_bw == CHANNEL_WIDTH_80) {
- center_ch = 7;
- } else if (chnl_bw == CHANNEL_WIDTH_40) {
+ if (chnl_bw == CHANNEL_WIDTH_40) {
if (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
center_ch = channel + 2;
else
center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
- if (bwmode == CHANNEL_WIDTH_80) {
- if (center_ch > channel)
- chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
- else if (center_ch < channel)
- chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
- else
- chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
- }
/* set Channel */
if (mutex_lock_interruptible(&(adapter_to_dvobj(padapter)->setch_mutex)))
if (phtpriv->ht_option == false)
return;
- if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)
- return;
-
if (pIE->Length > sizeof(struct HT_info_element))
return;
u8 query_ra_short_GI(struct sta_info *psta)
{
- u8 sgi = false, sgi_20m = false, sgi_40m = false, sgi_80m = false;
+ u8 sgi = false, sgi_20m = false, sgi_40m = false;
sgi_20m = psta->htpriv.sgi_20m;
sgi_40m = psta->htpriv.sgi_40m;
switch (psta->bw_mode) {
- case CHANNEL_WIDTH_80:
- sgi = sgi_80m;
- break;
case CHANNEL_WIDTH_40:
sgi = sgi_40m;
break;
)
{
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
- u8 i = 0; /* default set to 1S */
u8 txPower = 0;
u8 chnlIdx = (Channel-1);
txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
}
- /* Willis suggest adopt BW 40M power index while in BW 80 mode */
- else if (BandWidth == CHANNEL_WIDTH_80) {
- if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
- if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];
- if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];
- if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
-
- }
} else {/* 3 ============================== 5 G ============================== */
if (MGN_6M <= Rate)
txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S];
- } else if (BandWidth == CHANNEL_WIDTH_80) { /* BW80-1S, BW80-2S */
- /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */
- u8 channel5G_80M[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
- for (i = 0; i < ARRAY_SIZE(channel5G_80M); ++i)
- if (channel5G_80M[i] == Channel)
- chnlIdx = i;
-
- txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
-
- if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S];
- if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S];
- if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S];
- if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S];
}
}
return 0;
case CHANNEL_WIDTH_40:
return 1;
- case CHANNEL_WIDTH_80:
- return 2;
- case CHANNEL_WIDTH_160:
- return 3;
default:
return -1;
}
enum { /* tag_Bandwidth_Definition */
ODM_BW20M = 0,
ODM_BW40M = 1,
- ODM_BW80M = 2,
- ODM_BW160M = 3,
- ODM_BW10M = 4,
};
/* ODM_CMNINFO_BOARD_TYPE */
IGI_target = pDM_Odm->IGI_Base;
else if (*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = pDM_Odm->IGI_Base + 2;
- else if (*pDM_Odm->pBandWidth == ODM_BW80M)
- IGI_target = pDM_Odm->IGI_Base + 2;
else
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = (u8) IGI_target;
u8 BWSettingOfDesc = 0;
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
- if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
- if (pattrib->bwmode == CHANNEL_WIDTH_80)
- BWSettingOfDesc = 2;
- else if (pattrib->bwmode == CHANNEL_WIDTH_40)
- BWSettingOfDesc = 1;
- else
- BWSettingOfDesc = 0;
- } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
- if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
+ if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
+ if (pattrib->bwmode == CHANNEL_WIDTH_40)
BWSettingOfDesc = 1;
else
BWSettingOfDesc = 0;
u8 SCSettingOfDesc = 0;
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
- if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
- if (pattrib->bwmode == CHANNEL_WIDTH_80) {
- SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
- } else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
- if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
- SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
- else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
- SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
- } else {
- if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
- SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
- else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
- SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
- else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
- SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
- else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
- SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
- }
- } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
+ if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
if (pattrib->bwmode == CHANNEL_WIDTH_40) {
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
} else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
break;
- case CHANNEL_WIDTH_80:
- u2tmp = RegRfMod_BW | BIT8;
- rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
- break;
-
default:
break;
}
u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
- if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
- if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
- SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
- else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
- SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
-
- if (
- (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
- (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
- )
- SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
- else if (
- (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
- )
- SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
- else if (
- (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
- (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
- )
- SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
- else if (
- (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
- )
- SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
- } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
+ if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
struct wlan_bssid_ex dev_network;
u8 ht_enable;
- /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
- /* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
- /* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
+ /*
+ * 0: 20 MHz, 1: 40 MHz
+ * 2.4G use bit 0 ~ 3
+ * 0x01 means enable 2.4G 40MHz
+ */
u8 bw_mode;
u8 ampdu_enable;/* for tx */
u8 rx_stbc;
enum channel_width {
CHANNEL_WIDTH_20 = 0,
CHANNEL_WIDTH_40 = 1,
- CHANNEL_WIDTH_80 = 2,
- CHANNEL_WIDTH_160 = 3,
- CHANNEL_WIDTH_80_80 = 4,
- CHANNEL_WIDTH_MAX = 5,
};
/* Represent Extension Channel Offset in HT Capabilities */
static int rtw_uapsd_acvo_en;
int rtw_ht_enable = 1;
-/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz */
-/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
-/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
-static int rtw_bw_mode = 0x21;
+/*
+ * 0: 20 MHz, 1: 40 MHz
+ * 2.4G use bit 0 ~ 3
+ * 0x01 means enable 2.4G 40MHz
+ */
+static int rtw_bw_mode = 0x01;
static int rtw_ampdu_enable = 1;/* for enable tx_ampdu ,0: disable, 0x1:enable (but wifi_spec should be 0), 0x2: force enable (don't care wifi_spec) */
static int rtw_rx_stbc = 1;/* 0: disable, 1:enable 2.4g */
static int rtw_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */