drm/xe/dg2: Wa_18028616096 now applies to all DG2

The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231115183029.2649992-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index d03e667..6572715 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -403,12 +403,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                             PERF_FIX_BALANCING_CFE_DISABLE))
        },
        { XE_RTP_NAME("18028616096"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
-       },
-       { XE_RTP_NAME("18028616096"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G12),
+         XE_RTP_RULES(PLATFORM(DG2),
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
        },