drm/amd/display: add vline time in micro sec to PSR context

[why]
The current PSR SU programming margin is fixed base on FHD 60HZ
panel. If the resolution and refresh rate become higher, the time
of current margin might not cover the programming SU time.

[how]
Notice that the programming SU time is the same among different
panels.

Instead of fixing the margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index dc1d75b..68e9fc6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3274,6 +3274,8 @@ bool dc_link_setup_psr(struct dc_link *link,
                        psr_config->su_granularity_required;
                psr_context->su_y_granularity =
                        psr_config->su_y_granularity;
+               psr_context->line_time_in_us =
+                       psr_config->line_time_in_us;
        }
 
        psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d61ea3e..119ce8b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -676,6 +676,7 @@ struct psr_config {
        bool su_granularity_required;
        /* psr2 selective update y granularity capability */
        uint8_t su_y_granularity;
+       unsigned int line_time_in_us;
 };
 
 union dmcu_psr_level {
@@ -783,6 +784,7 @@ struct psr_context {
        bool su_granularity_required;
        /* psr2 selective update y granularity capability */
        uint8_t su_y_granularity;
+       unsigned int line_time_in_us;
 };
 
 struct colorspace_transform {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index bc49432..c2d6575 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -340,6 +340,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
                copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
 
        copy_settings_data->line_capture_indication = 0;
+       copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
        copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
        copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
        copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;