};
static const u32 hpd_gen11[HPD_NUM_PINS] = {
- [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
- [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
- [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
- [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
- [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
- [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
- [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
- [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
- [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
- [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
- [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
- [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
};
static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
{
switch (pin) {
case HPD_PORT_TC1:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
case HPD_PORT_TC2:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
case HPD_PORT_TC3:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
case HPD_PORT_TC4:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
case HPD_PORT_TC5:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
case HPD_PORT_TC6:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
default:
return false;
}
{
switch (pin) {
case HPD_PORT_TC1:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
case HPD_PORT_TC2:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
case HPD_PORT_TC3:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
case HPD_PORT_TC4:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
case HPD_PORT_TC5:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
case HPD_PORT_TC6:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
default:
return false;
}
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
} else {
drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
"Unrecognized PCH type 0x%x\n",
static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
}
/*
u32 hotplug;
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+ GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
}
icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
} else if (HAS_PCH_MCC(dev_priv)) {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
} else {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
#define GEN11_DE_HPD_IIR _MMIO(0x44478)
#define GEN11_DE_HPD_IER _MMIO(0x4447c)
#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \
- GEN11_TC_HOTPLUG(PORT_TC5) | \
- GEN11_TC_HOTPLUG(PORT_TC4) | \
- GEN11_TC_HOTPLUG(PORT_TC3) | \
- GEN11_TC_HOTPLUG(PORT_TC2) | \
- GEN11_TC_HOTPLUG(PORT_TC1))
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_6) | \
+ GEN11_TC_HOTPLUG(TC_PORT_5) | \
+ GEN11_TC_HOTPLUG(TC_PORT_4) | \
+ GEN11_TC_HOTPLUG(TC_PORT_3) | \
+ GEN11_TC_HOTPLUG(TC_PORT_2) | \
+ GEN11_TC_HOTPLUG(TC_PORT_1))
#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \
- GEN11_TBT_HOTPLUG(PORT_TC5) | \
- GEN11_TBT_HOTPLUG(PORT_TC4) | \
- GEN11_TBT_HOTPLUG(PORT_TC3) | \
- GEN11_TBT_HOTPLUG(PORT_TC2) | \
- GEN11_TBT_HOTPLUG(PORT_TC1))
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_6) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_5) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_4) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_3) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_2) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_1))
#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_1))
#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
SDE_DDI_HOTPLUG_ICP(PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_1))
#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
SDE_DDI_HOTPLUG_ICP(PORT_C) | \
SDE_DDI_HOTPLUG_ICP(PORT_B) | \
#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
- ICP_TC_HPD_ENABLE(PORT_TC3) | \
- ICP_TC_HPD_ENABLE(PORT_TC2) | \
- ICP_TC_HPD_ENABLE(PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_4) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_3) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_2) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_1))
#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
- ICP_TC_HPD_ENABLE(PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_6) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_5) | \
ICP_TC_HPD_ENABLE_MASK)
#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
(tc_port) + 12 : \
- (tc_port) - PORT_TC4 + 21))
+ (tc_port) - TC_PORT_4 + 21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))