drm/bridge: tc358767: Fix order of register defines

0x0510 is bigger than 0x50c, order them accordingly.
No functional change intended.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20231212075257.75084-3-alexander.stein@ew.tq-group.com

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index b8b29b2..637d38e 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -116,13 +116,6 @@
 /* System */
 #define TC_IDREG               0x0500
 #define SYSSTAT                        0x0508
-#define SYSCTRL                        0x0510
-#define DP0_AUDSRC_NO_INPUT            (0 << 3)
-#define DP0_AUDSRC_I2S_RX              (1 << 3)
-#define DP0_VIDSRC_NO_INPUT            (0 << 0)
-#define DP0_VIDSRC_DSI_RX              (1 << 0)
-#define DP0_VIDSRC_DPI_RX              (2 << 0)
-#define DP0_VIDSRC_COLOR_BAR           (3 << 0)
 #define SYSRSTENB              0x050c
 #define ENBI2C                         (1 << 0)
 #define ENBLCD0                                (1 << 2)
@@ -130,6 +123,13 @@
 #define ENBDSIRX                       (1 << 4)
 #define ENBREG                         (1 << 5)
 #define ENBHDCP                                (1 << 8)
+#define SYSCTRL                        0x0510  /* System Control Register */
+#define DP0_AUDSRC_NO_INPUT            (0 << 3)
+#define DP0_AUDSRC_I2S_RX              (1 << 3)
+#define DP0_VIDSRC_NO_INPUT            (0 << 0)
+#define DP0_VIDSRC_DSI_RX              (1 << 0)
+#define DP0_VIDSRC_DPI_RX              (2 << 0)
+#define DP0_VIDSRC_COLOR_BAR           (3 << 0)
 #define GPIOM                  0x0540
 #define GPIOC                  0x0544
 #define GPIOO                  0x0548