clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region

These clocks locate in VO and VPU GRF, serving for SD/SDIO controller
tuning purpose. Add their definitions and register them in driver if
corresponding GRF is available.

GRFs are looked up by compatible to simplify devicetree binding.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250506092206.46143-4-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c
index b8b577b..f5f1049 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3528.c
+++ b/drivers/clk/rockchip/clk-rk3528.c
@@ -10,6 +10,8 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/minmax.h>
 
 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
 
@@ -1061,23 +1063,65 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = {
                        0, 1, 1),
 };
 
+static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = {
+       MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0",
+                       RK3528_SDMMC_CON(0), 1, grf_type_vo),
+       MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0",
+                       RK3528_SDMMC_CON(1), 1, grf_type_vo),
+};
+
+static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = {
+       MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0",
+                       RK3528_SDIO0_CON(0), 1, grf_type_vpu),
+       MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0",
+                       RK3528_SDIO0_CON(1), 1, grf_type_vpu),
+       MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1",
+                       RK3528_SDIO1_CON(0), 1, grf_type_vpu),
+       MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1",
+                       RK3528_SDIO1_CON(1), 1, grf_type_vpu),
+};
+
 static int __init clk_rk3528_probe(struct platform_device *pdev)
 {
-       struct rockchip_clk_provider *ctx;
+       unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches);
+       unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches);
+       unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
+       unsigned long nr_clks, nr_vo_clks, nr_vpu_clks;
+       struct rockchip_aux_grf *vo_grf_e, *vpu_grf_e;
+       struct regmap *vo_grf, *vpu_grf;
        struct device *dev = &pdev->dev;
        struct device_node *np = dev->of_node;
-       unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
-       unsigned long nr_clks;
+       struct rockchip_clk_provider *ctx;
        void __iomem *reg_base;
 
-       nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
-                                              nr_branches) + 1;
-
        reg_base = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(reg_base))
                return dev_err_probe(dev, PTR_ERR(reg_base),
                                     "could not map cru region");
 
+       nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
+                                              nr_branches) + 1;
+
+       vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf");
+       if (!IS_ERR(vo_grf)) {
+               nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches,
+                                                         nr_vo_branches) + 1;
+               nr_clks = max(nr_clks, nr_vo_clks);
+       } else if (PTR_ERR(vo_grf) != -ENODEV) {
+               return dev_err_probe(dev, PTR_ERR(vo_grf),
+                                    "failed to look up VO GRF\n");
+       }
+
+       vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf");
+       if (!IS_ERR(vpu_grf)) {
+               nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches,
+                                                          nr_vpu_branches) + 1;
+               nr_clks = max(nr_clks, nr_vpu_clks);
+       } else if (PTR_ERR(vpu_grf) != -ENODEV) {
+               return dev_err_probe(dev, PTR_ERR(vpu_grf),
+                                    "failed to look up VPU GRF\n");
+       }
+
        ctx = rockchip_clk_init(np, reg_base, nr_clks);
        if (IS_ERR(ctx))
                return dev_err_probe(dev, PTR_ERR(ctx),
@@ -1092,6 +1136,32 @@ static int __init clk_rk3528_probe(struct platform_device *pdev)
                                     ARRAY_SIZE(rk3528_cpuclk_rates));
        rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
 
+       if (!IS_ERR(vo_grf)) {
+               vo_grf_e = devm_kzalloc(dev, sizeof(*vo_grf_e), GFP_KERNEL);
+               if (!vo_grf_e)
+                       return -ENOMEM;
+
+               vo_grf_e->grf   = vo_grf;
+               vo_grf_e->type  = grf_type_vo;
+               hash_add(ctx->aux_grf_table, &vo_grf_e->node, grf_type_vo);
+
+               rockchip_clk_register_branches(ctx, rk3528_vo_clk_branches,
+                                              nr_vo_branches);
+       }
+
+       if (!IS_ERR(vpu_grf)) {
+               vpu_grf_e = devm_kzalloc(dev, sizeof(*vpu_grf_e), GFP_KERNEL);
+               if (!vpu_grf_e)
+                       return -ENOMEM;
+
+               vpu_grf_e->grf  = vpu_grf;
+               vpu_grf_e->type = grf_type_vpu;
+               hash_add(ctx->aux_grf_table, &vpu_grf_e->node, grf_type_vpu);
+
+               rockchip_clk_register_branches(ctx, rk3528_vpu_clk_branches,
+                                              nr_vpu_branches);
+       }
+
        rk3528_rst_init(np, reg_base);
 
        rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index d411de7..10be168 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -218,6 +218,9 @@ struct clk;
 #define RK3528_CLKSEL_CON(x)           ((x) * 0x4 + 0x300)
 #define RK3528_CLKGATE_CON(x)          ((x) * 0x4 + 0x800)
 #define RK3528_SOFTRST_CON(x)          ((x) * 0x4 + 0xa00)
+#define RK3528_SDMMC_CON(x)            ((x) * 0x4 + 0x24)
+#define RK3528_SDIO0_CON(x)            ((x) * 0x4 + 0x4)
+#define RK3528_SDIO1_CON(x)            ((x) * 0x4 + 0xc)
 #define RK3528_PMU_CLKSEL_CON(x)       ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
 #define RK3528_PMU_CLKGATE_CON(x)      ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
 #define RK3528_PCIE_CLKSEL_CON(x)      ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
@@ -446,6 +449,8 @@ enum rockchip_grf_type {
        grf_type_pmu0,
        grf_type_pmu1,
        grf_type_ioc,
+       grf_type_vo,
+       grf_type_vpu,
 };
 
 /* ceil(sqrt(enums in rockchip_grf_type - 1)) */