drm/amdgpu: Fix S3 test issue

During S3 test, when system wake up and resume, ras interface
is already allocated. Move workaround before ras jumps to resume
step in gfx_v9_0_ecc_late_init, and make sure workaround applied
during resume. Also remove unused mmGB_EDC_MODE clearing.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc6d8c1..d07f3dd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3632,7 +3632,6 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
        struct amdgpu_ib ib;
        struct dma_fence *f = NULL;
        int r, i, j;
-       u32 tmp;
        unsigned total_size, vgpr_offset, sgpr_offset;
        u64 gpu_addr;
 
@@ -3644,9 +3643,6 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
        if (!ring->sched.ready)
                return 0;
 
-       tmp = RREG32_SOC15(GC, 0, mmGB_EDC_MODE);
-       WREG32_SOC15(GC, 0, mmGB_EDC_MODE, 0);
-
        total_size =
                ((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
        total_size +=
@@ -3812,6 +3808,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
                return 0;
        }
 
+       /* requires IBs so do in late init after IB pool is initialized */
+       r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+       if (r)
+               return r;
+
        if (*ras_if)
                goto resume;
 
@@ -3819,11 +3820,6 @@ static int gfx_v9_0_ecc_late_init(void *handle)
        if (!*ras_if)
                return -ENOMEM;
 
-       /* requires IBs so do in late init after IB pool is initialized */
-       r = gfx_v9_0_do_edc_gpr_workarounds(adev);
-       if (r)
-               return r;
-
        **ras_if = ras_block;
 
        r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);