drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2

Introduce the register bits to enable the 3rd DSC engine VDSC2.
Add support to read/write these bits.

v2: Only introduce bits that are used and update the subject and commit
message. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-5-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index bd6480e..053f1d1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -775,6 +775,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
                dss_ctl2_val |= VDSC1_ENABLE;
                dss_ctl1_val |= JOINER_ENABLE;
        }
+
+       if (vdsc_instances_per_pipe > 2) {
+               dss_ctl2_val |= VDSC2_ENABLE;
+               dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
+       }
+
        if (crtc_state->joiner_pipes) {
                if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
                        dss_ctl1_val |= ULTRA_JOINER_ENABLE;
@@ -976,7 +982,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
        if (!crtc_state->dsc.compression_enable)
                goto out;
 
-       if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
+       if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
+               crtc_state->dsc.num_streams = 3;
+       else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
                crtc_state->dsc.num_streams = 2;
        else
                crtc_state->dsc.num_streams = 1;

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index d7a72b9..474a7f9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -22,6 +22,8 @@
 
 #define DSS_CTL2                               _MMIO(0x67404)
 #define  VDSC0_ENABLE                          REG_BIT(31)
+#define  VDSC2_ENABLE                          REG_BIT(30)
+#define  SMALL_JOINER_CONFIG_3_ENGINES         REG_BIT(23)
 #define  VDSC1_ENABLE                          REG_BIT(15)
 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK                (0xfff << 0)
 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)     ((pixels) << 0)