drm/amd/display: add debug option to bypass ssinfo from bios.
authorCharlene Liu <Charlene.Liu@amd.com>
Sat, 12 Feb 2022 01:55:25 +0000 (20:55 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Feb 2022 19:26:35 +0000 (14:26 -0500)
[Why&How]
add debug option to bypass ssinfo from bios.

Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dc.h

index b210f8e..dfba613 100644 (file)
@@ -374,6 +374,8 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
                                clk_mgr_dce->dprefclk_ss_percentage =
                                                info.spread_spectrum_percentage;
                        }
+                       if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
+                               clk_mgr_dce->dprefclk_ss_percentage = 0;
                }
        }
 }
index e17c993..59fdd7f 100644 (file)
@@ -697,6 +697,8 @@ void dcn31_clk_mgr_construct(
        clk_mgr->base.base.dprefclk_khz = 600000;
        clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
        dce_clock_read_ss_info(&clk_mgr->base);
+       /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
+       //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
 
        clk_mgr->base.base.bw_params = &dcn31_bw_params;
 
index 9fa87a4..c5a36c8 100644 (file)
@@ -709,6 +709,7 @@ struct dc_debug_options {
        union dpia_debug_options dpia_debug;
 #endif
        bool apply_vendor_specific_lttpr_wa;
+       bool ignore_dpref_ss;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;