rtw89: 8852c: rfk: add RCK
authorPing-Ke Shih <pkshih@realtek.com>
Mon, 2 May 2022 23:54:05 +0000 (07:54 +0800)
committerKalle Valo <kvalo@kernel.org>
Tue, 3 May 2022 05:32:02 +0000 (08:32 +0300)
RCK is synchronize RC calibration. It needs to be triggered only once when
interface is going to up.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220502235408.15052-6-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.h

index 3640648..6db61e6 100644 (file)
@@ -1777,6 +1777,7 @@ static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
        memset(mcc_info, 0, sizeof(*mcc_info));
        rtw8852c_lck_init(rtwdev);
 
+       rtw8852c_rck(rtwdev);
        rtw8852c_dack(rtwdev);
 }
 
index 974bb57..4025245 100644 (file)
@@ -470,6 +470,41 @@ static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
        rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
 }
 
+static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+       u32 rf_reg5, rck_val = 0;
+       u32 val;
+       int ret;
+
+       rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
+
+       rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
+
+       rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
+       rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
+
+       rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n",
+                   rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
+
+       /* RCK trigger */
+       rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
+
+       ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 20,
+                                      false, rtwdev, path, 0x1c, BIT(3));
+       if (ret)
+               rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n");
+
+       rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
+       rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
+
+       rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
+
+       rtw89_debug(rtwdev, RTW89_DBG_RFK,
+                   "[RCK] RF 0x1b / 0x1c = 0x%x / 0x%x\n",
+                   rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK),
+                   rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK));
+}
+
 static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
                          enum rtw89_rf_path path)
 {
@@ -1619,6 +1654,14 @@ void rtw8852c_set_channel_rf(struct rtw89_dev *rtwdev,
                            param->bandwidth);
 }
 
+void rtw8852c_rck(struct rtw89_dev *rtwdev)
+{
+       u8 path;
+
+       for (path = 0; path < 2; path++)
+               _rck(rtwdev, path);
+}
+
 void rtw8852c_dack(struct rtw89_dev *rtwdev)
 {
        u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0);
index a16ad93..faacdf1 100644 (file)
@@ -7,6 +7,7 @@
 
 #include "core.h"
 
+void rtw8852c_rck(struct rtw89_dev *rtwdev);
 void rtw8852c_dack(struct rtw89_dev *rtwdev);
 void rtw8852c_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
 void rtw8852c_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);