powerpc/perf: Fix unit_sel/cache_sel checks

Raw event code has couple of fields "unit" and "cache" in it, to capture
the "unit" to monitor for a given pmcxsel and cache reload qualifier to
program in MMCR1.

isa207_get_constraint() refers "unit" field to update the MMCRC (L2/L3)
Event bus control fields with "cache" bits of the raw event code.
These are power8 specific and not supported by PowerISA v3.0 pmu. So wrap
the checks to be power8 specific. Also, "cache" bit field is referred to
update MMCR1[16:17] and this check can be power8 specific.

Fixes: 7ffd948fae4cd ('powerpc/perf: factor out power8 pmu functions')
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 6a2f65d..053b8e9 100644 (file)
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -148,6 +148,14 @@ static bool is_thresh_cmp_valid(u64 event)
        return true;
 }
 
+static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
+{
+       unsigned int cache;
+
+       cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
+       return cache;
+}
+
 static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
 {
        u64 ret = PERF_MEM_NA;
@@ -288,10 +296,10 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
                 * have a cache selector of zero. The bank selector (bit 3) is
                 * irrelevant, as long as the rest of the value is 0.
                 */
-               if (cache & 0x7)
+               if (!cpu_has_feature(CPU_FTR_ARCH_300) && (cache & 0x7))
                        return -1;
 
-       } else if (event & EVENT_IS_L1) {
+       } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
                mask  |= CNST_L1_QUAL_MASK;
                value |= CNST_L1_QUAL_VAL(cache);
        }
@@ -394,11 +402,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
                /* In continuous sampling mode, update SDAR on TLB miss */
                mmcra_sdar_mode(event[i], &mmcra);
 
-               if (event[i] & EVENT_IS_L1) {
-                       cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
-                       mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
-                       cache >>= 1;
-                       mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
+               if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+                       cache = dc_ic_rld_quad_l1_sel(event[i]);
+                       mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
+               } else {
+                       if (event[i] & EVENT_IS_L1) {
+                               cache = dc_ic_rld_quad_l1_sel(event[i]);
+                               mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
+                       }
                }
 
                if (is_event_marked(event[i])) {

diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 0028f4b..e5a6216 100644 (file)
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -163,8 +163,8 @@
 #define MMCR1_COMBINE_SHIFT(pmc)       (35 - ((pmc) - 1))
 #define MMCR1_PMCSEL_SHIFT(pmc)                (24 - (((pmc) - 1)) * 8)
 #define MMCR1_FAB_SHIFT                        36
-#define MMCR1_DC_QUAL_SHIFT            47
-#define MMCR1_IC_QUAL_SHIFT            46
+#define MMCR1_DC_IC_QUAL_MASK          0x3
+#define MMCR1_DC_IC_QUAL_SHIFT         46
 
 /* MMCR1 Combine bits macro for power9 */
 #define p9_MMCR1_COMBINE_SHIFT(pmc)    (38 - ((pmc - 1) * 2))