drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams

The port PLL selection needs to be up-to-date in the CRTC state of both
the primary and all secondary MST streams. The commit removing the
encoder update_prepare/complete hooks (see Fixes: below), stopped doing
this for secondary streams, fix this up.

Fixes: 0f752b2178c9 ("drm/i915: Remove the encoder update_prepare()/complete() hooks")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8336
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230414173800.590790-1-imre.deak@intel.com
(cherry picked from commit 27ac123b454417ea92d77c13a5d94655f53b759c)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d0bb3a5..3a7b988 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3060,6 +3060,25 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
        intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
 }
 
+void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
+                                 struct intel_encoder *encoder,
+                                 struct intel_crtc *crtc)
+{
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       struct intel_crtc_state *crtc_state =
+               intel_atomic_get_new_crtc_state(state, crtc);
+       struct intel_crtc *slave_crtc;
+       enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+       if (!intel_phy_is_tc(i915, phy))
+               return;
+
+       intel_update_active_dpll(state, crtc, encoder);
+       for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
+                                        intel_crtc_bigjoiner_slave_pipes(crtc_state))
+               intel_update_active_dpll(state, slave_crtc, encoder);
+}
+
 static void
 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
                         struct intel_encoder *encoder,
@@ -3074,15 +3093,9 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
        if (is_tc_port) {
                struct intel_crtc *master_crtc =
                        to_intel_crtc(crtc_state->uapi.crtc);
-               struct intel_crtc *slave_crtc;
 
                intel_tc_port_get_link(dig_port, crtc_state->lane_count);
-
-               intel_update_active_dpll(state, master_crtc, encoder);
-
-               for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
-                                                intel_crtc_bigjoiner_slave_pipes(crtc_state))
-                       intel_update_active_dpll(state, slave_crtc, encoder);
+               intel_ddi_update_active_dpll(state, encoder, master_crtc);
        }
 
        main_link_aux_power_domain_get(dig_port, crtc_state);

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index c85e74a..2bc0340 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -72,5 +72,8 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
 int intel_ddi_level(struct intel_encoder *encoder,
                    const struct intel_crtc_state *crtc_state,
                    int lane);
+void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
+                                 struct intel_encoder *encoder,
+                                 struct intel_crtc *crtc);
 
 #endif /* __INTEL_DDI_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a88b852..2c49d9a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -674,6 +674,13 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
        if (intel_dp->active_mst_links == 0)
                dig_port->base.pre_pll_enable(state, &dig_port->base,
                                                    pipe_config, NULL);
+       else
+               /*
+                * The port PLL state needs to get updated for secondary
+                * streams as for the primary stream.
+                */
+               intel_ddi_update_active_dpll(state, &dig_port->base,
+                                            to_intel_crtc(pipe_config->uapi.crtc));
 }
 
 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,