soc: mediatek: pm-domains: Add support for Helio X10 MT6795

Add pm-domains (mtcmos) data for MediaTek Helio X10 MT6795 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220503141441.125852-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediatek/mt6795-pm-domains.h
new file mode 100644 (file)
index 0000000..ef07c9d
--- /dev/null
+++ b/drivers/soc/mediatek/mt6795-pm-domains.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mt6795-power.h>
+
+/*
+ * MT6795 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
+       [MT6795_POWER_DOMAIN_VDEC] = {
+               .name = "vdec",
+               .sta_mask = PWR_STATUS_VDEC,
+               .ctl_offs = SPM_VDE_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+       },
+       [MT6795_POWER_DOMAIN_VENC] = {
+               .name = "venc",
+               .sta_mask = PWR_STATUS_VENC,
+               .ctl_offs = SPM_VEN_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+       },
+       [MT6795_POWER_DOMAIN_ISP] = {
+               .name = "isp",
+               .sta_mask = PWR_STATUS_ISP,
+               .ctl_offs = SPM_ISP_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(13, 12),
+       },
+       [MT6795_POWER_DOMAIN_MM] = {
+               .name = "mm",
+               .sta_mask = PWR_STATUS_DISP,
+               .ctl_offs = SPM_DIS_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_infracfg = {
+                       BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
+                                              MT8173_TOP_AXI_PROT_EN_MM_M1),
+               },
+       },
+       [MT6795_POWER_DOMAIN_MJC] = {
+               .name = "mjc",
+               .sta_mask = BIT(20),
+               .ctl_offs = 0x298,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+       },
+       [MT6795_POWER_DOMAIN_AUDIO] = {
+               .name = "audio",
+               .sta_mask = PWR_STATUS_AUDIO,
+               .ctl_offs = SPM_AUDIO_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+       },
+       [MT6795_POWER_DOMAIN_MFG_ASYNC] = {
+               .name = "mfg_async",
+               .sta_mask = PWR_STATUS_MFG_ASYNC,
+               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = 0,
+       },
+       [MT6795_POWER_DOMAIN_MFG_2D] = {
+               .name = "mfg_2d",
+               .sta_mask = PWR_STATUS_MFG_2D,
+               .ctl_offs = SPM_MFG_2D_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(13, 12),
+       },
+       [MT6795_POWER_DOMAIN_MFG] = {
+               .name = "mfg",
+               .sta_mask = PWR_STATUS_MFG,
+               .ctl_offs = SPM_MFG_PWR_CON,
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+               .sram_pdn_bits = GENMASK(13, 8),
+               .sram_pdn_ack_bits = GENMASK(21, 16),
+               .bp_infracfg = {
+                       BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
+                                              MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+                                              MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+                                              MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+               },
+       },
+};
+
+static const struct scpsys_soc_data mt6795_scpsys_data = {
+       .domains_data = scpsys_domain_data_mt6795,
+       .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6795),
+};
+
+#endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */

diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index a3dae39..9734f10 100644 (file)
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -16,6 +16,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/soc/mediatek/infracfg.h>
 
+#include "mt6795-pm-domains.h"
 #include "mt8167-pm-domains.h"
 #include "mt8173-pm-domains.h"
 #include "mt8183-pm-domains.h"
@@ -558,6 +559,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
 }
 
 static const struct of_device_id scpsys_of_match[] = {
+       {
+               .compatible = "mediatek,mt6795-power-controller",
+               .data = &mt6795_scpsys_data,
+       },
        {
                .compatible = "mediatek,mt8167-power-controller",
                .data = &mt8167_scpsys_data,