extern void au1xxx_timer_setup(struct irqaction *irq);
extern void set_cpuspec(void);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
struct cpu_spec *sp;
char *argptr;
.io_offset = 0 - GT64111_IO_BASE
};
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
set_io_port_base(NILE4_PCI_IO_BASE);
isa_slot_offset = NILE4_PCI_MEM_BASE;
static void ddb5476_board_init(void);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
extern struct pci_controller ddb5477_ext_controller;
extern struct pci_controller ddb5477_io_controller;
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
/* initialize board - we don't trust the loader */
ddb5477_board_init();
extern void dec_time_init(void);
extern void dec_timer_setup(struct irqaction *);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
board_be_init = dec_be_init;
board_time_init = dec_time_init;
unsigned char mac_0_1[12];
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int config = read_c0_config();
unsigned int status = read_c0_status();
*/
extern void gt64120_time_init(void);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
_machine_restart = galileo_machine_restart;
_machine_halt = galileo_machine_halt;
gt64120_base = 0xe0000000;
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
unsigned int tmpword;
it8172_resources.ram.end = memsize;
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned short dsr;
char *argptr;
{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
};
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
int i;
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
char *argptr;
#endif /* CONFIG_BLK_DEV_INITRD */
}
+/*
+ * arch_mem_init - initialize memory managment subsystem
+ *
+ * o plat_mem_setup() detects the memory configuration and will record detected
+ * memory areas using add_memory_region.
+ * o parse_cmdline_early() parses the command line for mem= options which,
+ * iff detected, will override the results of the automatic detection.
+ *
+ * At this stage the memory configuration of the system is known to the
+ * kernel but generic memory managment system is still entirely uninitialized.
+ *
+ * o bootmem_init()
+ * o sparse_init()
+ * o paging_init()
+ *
+ * At this stage the bootmem allocator is ready to use.
+ *
+ * NOTE: historically plat_mem_setup did the entire platform initialization.
+ * This was rather impractical because it meant plat_mem_setup had to
+ * get away without any kind of memory allocator. To keep old code from
+ * breaking plat_setup was just renamed to plat_setup and a second platform
+ * initialization hook for anything else was introduced.
+ */
+
+extern void plat_mem_setup(void);
+
+static void __init arch_mem_init(char **cmdline_p)
+{
+ /* call board setup routine */
+ plat_mem_setup();
+
+ strlcpy(command_line, arcs_cmdline, sizeof(command_line));
+ strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
+
+ *cmdline_p = command_line;
+
+ parse_cmdline_early();
+ bootmem_init();
+ sparse_init();
+ paging_init();
+}
+
static inline void resource_init(void)
{
int i;
#undef MAXMEM
#undef MAXMEM_PFN
-extern void plat_setup(void);
-
void __init setup_arch(char **cmdline_p)
{
cpu_probe();
#endif
#endif
- /* call board setup routine */
- plat_setup();
+ arch_mem_init(cmdline_p);
- strlcpy(command_line, arcs_cmdline, sizeof(command_line));
- strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
-
- *cmdline_p = command_line;
-
- parse_cmdline_early();
- bootmem_init();
- sparse_init();
- paging_init();
resource_init();
#ifdef CONFIG_SMP
plat_smp_setup();
}
#endif
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
int i;
lasat_misc = &lasat_misc_info[mips_machtype];
return "MIPS Atlas";
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
mips_pcibios_init();
}
#endif
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int i;
return "MIPS SEAD";
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
ioport_resource.end = 0x7fffffff;
return "MIPSsim";
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
set_io_port_base(0xbfd00000);
arch_initcall(ja_pci_init);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int tmpword;
arch_initcall(ja_pci_init);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int tmpword;
rtc_mips_set_time = m48t37y_set_time;
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int tmpword;
printk("Done\n");
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
unsigned int tmpword;
int pnx8550_console_port = -1;
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
int i;
char* argptr;
py_rtc_setup();
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
board_time_init = yosemite_time_init;
late_time_init = py_late_time_init;
setup_irq(0, irq);
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
set_io_port_base(QEMU_PORT_BASE);
board_timer_setup = qemu_timer_setup;
extern void ip22_be_init(void) __init;
extern void ip22_time_init(void) __init;
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
char *ctype;
char *cserial;
extern void ip27_time_init(void);
extern void ip27_reboot_setup(void);
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
hubreg_t p, e, n_mode;
nasid_t nid;
setup_irq(IP32_R4K_TIMER_IRQ, irq);
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
board_be_init = ip32_be_init;
return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
bcm1480_setup();
rtc_mips_set_time = mc146818_set_rtc_mmss;
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
sni_pcimt_detect();
sni_pcimt_sc_init();
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
board_time_init = tx4927_time_init;
board_timer_setup = tx4927_timer_setup;
}
void __init
-plat_setup(void)
+plat_mem_setup(void)
{
board_time_init = tx4938_time_init;
board_timer_setup = tx4938_timer_setup;
board_timer_setup = setup_timer_irq;
}
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
{
vr41xx_calculate_clock_frequency();
* Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
+
+/*
+ * Platform memory detection hook called by setup_arch
+ */
+extern void plat_mem_setup(void);
+
#endif /* _ASM_BOOTINFO_H */