clk: renesas: r9a09g047: Add XSPI clock/reset

Add XSPI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index be38754..2169999 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -35,6 +35,7 @@ enum clk_ids {
        CLK_PLLCM33_DIV4,
        CLK_PLLCM33_DIV5,
        CLK_PLLCM33_DIV16,
+       CLK_PLLCM33_GEAR,
        CLK_SMUX2_XSPI_CLK0,
        CLK_SMUX2_XSPI_CLK1,
        CLK_PLLCM33_XSPI,
@@ -107,6 +108,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
        DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
 
+       DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
+
        DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
        DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
        DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
@@ -135,6 +138,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
                 CDDIV1_DIVCTL3, dtable_1_8),
        DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+       DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
 };
 
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -180,6 +184,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(10, BIT(14))),
        DEF_MOD("canfd_0_clkc",                 CLK_PLLCLN_DIV20, 9, 14, 4, 30,
                                                BUS_MSTOP(10, BIT(14))),
+       DEF_MOD("spi_hclk",                     CLK_PLLCM33_GEAR, 9, 15, 4, 31,
+                                               BUS_MSTOP(4, BIT(5))),
+       DEF_MOD("spi_aclk",                     CLK_PLLCM33_GEAR, 10, 0, 5, 0,
+                                               BUS_MSTOP(4, BIT(5))),
+       DEF_MOD_NO_PM("spi_clk_spix2",          CLK_PLLCM33_XSPI, 10, 1, 5, 2,
+                                               BUS_MSTOP(4, BIT(5))),
        DEF_MOD("sdhi_0_imclk",                 CLK_PLLCLN_DIV8, 10, 3, 5, 3,
                                                BUS_MSTOP(8, BIT(2))),
        DEF_MOD("sdhi_0_imclk2",                CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -240,6 +250,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(10, 0, 4, 17),          /* RIIC_8_MRST */
        DEF_RST(10, 1, 4, 18),          /* CANFD_0_RSTP_N */
        DEF_RST(10, 2, 4, 19),          /* CANFD_0_RSTC_N */
+       DEF_RST(10, 3, 4, 20),          /* SPI_HRESETN */
+       DEF_RST(10, 4, 4, 21),          /* SPI_ARESETN */
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */