drm/amd/display: Fix Silence signed/unsighed mismatch warning in dc

[Why]
Implicit signed-to-unsigned conversions caused compiler
warnings in DC paths.

[How]
Added explicit (unsigned int)/(uint32_t) casts for sentinel -1
assignments and IRQ ~MASK initializers, with small cast alignment
in logging/DPCD code.

Functionality and behavior is unchanged; only type intent is explicit.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
index 8c54c02..f37a43f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
@@ -2010,10 +2010,10 @@ static void calculate_bandwidth(
        }
        /*output link bit per pixel supported*/
        for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-               data->output_bpphdmi[k] = bw_def_na;
-               data->output_bppdp4_lane_hbr[k] = bw_def_na;
-               data->output_bppdp4_lane_hbr2[k] = bw_def_na;
-               data->output_bppdp4_lane_hbr3[k] = bw_def_na;
+               data->output_bpphdmi[k] = (uint32_t)bw_def_na;
+               data->output_bppdp4_lane_hbr[k] = (uint32_t)bw_def_na;
+               data->output_bppdp4_lane_hbr2[k] = (uint32_t)bw_def_na;
+               data->output_bppdp4_lane_hbr3[k] = (uint32_t)bw_def_na;
                if (data->enable[k]) {
                        data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
                        if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index d50b944..cd4c455 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -92,7 +92,7 @@ static int determine_sclk_from_bounding_box(
 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
 {
        uint8_t j;
-       uint32_t min_vertical_blank_time = -1;
+       uint32_t min_vertical_blank_time = (uint32_t)-1;
 
        for (j = 0; j < context->stream_count; j++) {
                struct dc_stream_state *stream = context->streams[j];

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 727bcf0..e95d5b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -5240,7 +5240,7 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
                return 64;
        default:
                ASSERT_CRITICAL(false);
-               return -1;
+               return UINT_MAX;
        }
 }
 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 5722be9..0791b91 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -610,7 +610,7 @@ static uint32_t dce112_get_pix_clk_dividers(
                        || pix_clk_params->requested_pix_clk_100hz == 0) {
                DC_LOG_ERROR(
                        "%s: Invalid parameters!!\n", __func__);
-               return -1;
+               return (uint32_t)-1;
        }
 
        memset(pll_settings, 0, sizeof(*pll_settings));
@@ -621,7 +621,7 @@ static uint32_t dce112_get_pix_clk_dividers(
                pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
                pll_settings->actual_pix_clk_100hz =
                                        pix_clk_params->requested_pix_clk_100hz;
-               return -1;
+               return (uint32_t)-1;
        }
 
        dce112_get_pix_clk_dividers_helper(clk_src,
@@ -1376,7 +1376,7 @@ static uint32_t dcn3_get_pix_clk_dividers(
                        || pix_clk_params->requested_pix_clk_100hz == 0) {
                DC_LOG_ERROR(
                        "%s: Invalid parameters!!\n", __func__);
-               return -1;
+               return UINT_MAX;
        }
 
        memset(pll_settings, 0, sizeof(*pll_settings));

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index dcd2cdf..c702a30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -381,10 +381,10 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx,
        }
 
        for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-               seg_distr[i] = -1;
+               seg_distr[i] = (uint32_t)-1;
 
        for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
-               if (seg_distr[k] != -1)
+               if (seg_distr[k] != (uint32_t)-1)
                        hw_points += (1 << seg_distr[k]);
        }
 
@@ -565,7 +565,7 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
 
 
        for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-               seg_distr[i] = -1;
+               seg_distr[i] = (uint32_t)-1;
        /* 12 segments
         * segments are from 2^-12 to 0
         */
@@ -573,7 +573,7 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
                seg_distr[i] = 4;
 
        for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
-               if (seg_distr[k] != -1)
+               if (seg_distr[k] != (uint32_t)-1)
                        hw_points += (1 << seg_distr[k]);
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
index a0d437f..f73c5f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
@@ -746,7 +746,7 @@ bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
                src_width, dest_width);
 
        if (dc_fixpt_floor(tmp_h_ratio_luma) == 8)
-               h_ratio_luma = -1;
+               h_ratio_luma = (uint32_t)-1;
        else
                h_ratio_luma = dc_fixpt_u3d19(tmp_h_ratio_luma) << 5;
 
@@ -824,7 +824,7 @@ bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
                src_height, dest_height);
 
        if (dc_fixpt_floor(tmp_v_ratio_luma) == 8)
-               v_ratio_luma = -1;
+               v_ratio_luma = (uint32_t)-1;
        else
                v_ratio_luma = dc_fixpt_u3d19(tmp_v_ratio_luma) << 5;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
index 227aa86..9dbccf5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
@@ -159,10 +159,10 @@ bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,
        }
 
        for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-               seg_distr[i] = -1;
+               seg_distr[i] = (uint32_t)-1;
 
        for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
-               if (seg_distr[k] != -1)
+               if (seg_distr[k] != (uint32_t)-1)
                        hw_points += (1 << seg_distr[k]);
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
index c5e8419..5679b79 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
@@ -76,7 +76,7 @@ struct _vcs_dpi_ip_params_st dcn1_0_ip = {
        .line_buffer_size_bits = 589824,
        .max_line_buffer_lines = 12,
        .IsLineBufferBppFixed = 0,
-       .LineBufferFixedBpp = -1,
+       .LineBufferFixedBpp = (unsigned int)-1,
        .writeback_luma_buffer_size_kbytes = 12,
        .writeback_chroma_buffer_size_kbytes = 8,
        .max_num_dpp = 4,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index d202577..e4bd608 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -488,15 +488,15 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
                seg_distr[8] = 4;
                seg_distr[9] = 4;
                seg_distr[10] = 0;
-               seg_distr[11] = -1;
-               seg_distr[12] = -1;
-               seg_distr[13] = -1;
-               seg_distr[14] = -1;
-               seg_distr[15] = -1;
+               seg_distr[11] = (uint32_t)-1;
+               seg_distr[12] = (uint32_t)-1;
+               seg_distr[13] = (uint32_t)-1;
+               seg_distr[14] = (uint32_t)-1;
+               seg_distr[15] = (uint32_t)-1;
        }
 
        for (k = 0; k < 16; k++) {
-               if (seg_distr[k] != -1)
+               if (seg_distr[k] != (uint32_t)-1)
                        hw_points += (1 << seg_distr[k]);
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 676df39..002b097 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -92,7 +92,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
                .enable_value = {\
                        DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
-                       ~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
+                       (uint32_t)~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
                },\
                .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
                .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
@@ -107,7 +107,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
                .enable_value = {\
                        DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
-                       ~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
+                       (uint32_t)~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
                .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
                .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
                .ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
@@ -121,7 +121,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
                .enable_value = {\
                        GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-                       ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
+                       (uint32_t)~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
                .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
                .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
                .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
@@ -136,7 +136,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
                .enable_value = {\
                        CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-                       ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
+                       (uint32_t)~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
                .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
                .ack_mask =\
                CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
@@ -152,7 +152,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
                .enable_value = {\
                        CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-                       ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+                       (uint32_t)~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
                .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
                .ack_mask =\
                CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index b473dae..dbab6e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -79,7 +79,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
index b5c5f42..3e19dfd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
@@ -68,7 +68,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
                .enable_value = {\
                        DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
-                       ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
+                       (uint32_t)~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
                },\
                .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
                .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
@@ -83,7 +83,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
                .enable_value = {\
                                DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
-                       ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
+                       (uint32_t)~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
                .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
                .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
                .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
@@ -98,7 +98,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
                .enable_value = {\
                        GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-                       ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
+                       (uint32_t)~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
                .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
                .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
                .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
@@ -113,7 +113,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
                .enable_value = {\
                        CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-                       ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
+                       (uint32_t)~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
                .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
                .ack_mask =\
                CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
@@ -129,7 +129,7 @@ static struct irq_source_info_funcs vupdate_irq_info_funcs = {
                CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
                .enable_value = {\
                        CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-                       ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+                       (uint32_t)~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
                .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
                .ack_mask =\
                CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
index ca2e137..113bd76 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
@@ -176,7 +176,7 @@ static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 1c4c51a..98eedca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -179,7 +179,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
index 9e08814..be02ca2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
@@ -189,7 +189,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index 92bcd35..fe830a5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -196,7 +196,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
index 16685d0..d77d51e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
@@ -180,7 +180,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
                .enable_value = {\
                                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-                               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+                               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
                },\
                .ack_reg = SRI(reg2, block, reg_num),\
                .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
@@ -199,7 +199,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
index 01d83e1..afe3d7d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
@@ -123,7 +123,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
                .enable_value = {\
                                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-                               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+                               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
                },\
                .ack_reg = SRI(reg2, block, reg_num),\
                .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
index 2114c56..5c86e95 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
@@ -184,7 +184,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -198,7 +198,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
index 16f158e..34aa7a0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
@@ -186,7 +186,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -200,7 +200,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c b/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
index 8ee03c0..f63990a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
@@ -191,7 +191,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -205,7 +205,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
index 07e6f7d..5d4d5ed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -195,7 +195,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -209,7 +209,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c b/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
index 3d28a50..05aeb6e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
@@ -184,7 +184,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base + reg_num].enable_value[0] = \
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base + reg_num].enable_value[1] = \
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
        REG_STRUCT[base + reg_num].ack_mask = \
                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
@@ -198,7 +198,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base].enable_value[0] = \
                reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base].enable_value[1] = \
-               ~reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
        REG_STRUCT[base].ack_mask = \
                reg2 ## __ ## mask2 ## _MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
index f716c25..9d835b6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
@@ -163,7 +163,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base + reg_num].enable_value[0] = \
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base + reg_num].enable_value[1] = \
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
        REG_STRUCT[base + reg_num].ack_mask = \
                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
@@ -177,7 +177,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base].enable_value[0] = \
                reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base].enable_value[1] = \
-               ~reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
        REG_STRUCT[base].ack_mask = \
                reg2 ## __ ## mask2 ## _MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c b/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
index e718004..3da9f01 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
@@ -162,7 +162,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base + reg_num].enable_value[0] = \
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base + reg_num].enable_value[1] = \
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
        REG_STRUCT[base + reg_num].ack_mask = \
                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
@@ -176,7 +176,7 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {
        REG_STRUCT[base].enable_value[0] = \
                reg1 ## __ ## mask1 ## _MASK,\
        REG_STRUCT[base].enable_value[1] = \
-               ~reg1 ## __ ## mask1 ## _MASK, \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
        REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
        REG_STRUCT[base].ack_mask = \
                reg2 ## __ ## mask2 ## _MASK,\

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
index 2cde50b..a12bb3c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
@@ -175,7 +175,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -189,7 +189,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
index 19e0741..bdf733d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
@@ -173,7 +173,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-               ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI(reg2, block, reg_num),\
        .ack_mask = \
@@ -187,7 +187,7 @@ static struct irq_source_info_funcs vline2_irq_info_funcs = {
                reg1 ## __ ## mask1 ## _MASK,\
        .enable_value = {\
                reg1 ## __ ## mask1 ## _MASK,\
-               ~reg1 ## __ ## mask1 ## _MASK \
+               (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
        },\
        .ack_reg = SRI_DMUB(reg2),\
        .ack_mask = \

diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
index 6bfd2c1..8b398b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
@@ -1428,7 +1428,7 @@ uint32_t mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx)
        }
 
        //no vacant RMU units or invalid parameters acquire_post_bldn_3dlut
-       return -1;
+       return (uint32_t)-1;
 }
 
 static int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index fdcf8db..d83a6be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -1039,7 +1039,7 @@ static bool dce100_resource_construct(
 
        pool->base.res_cap = &res_cap;
        pool->base.funcs = &dce100_res_pool_funcs;
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
 
        bp = ctx->dc_bios;
 
@@ -1111,7 +1111,7 @@ static bool dce100_resource_construct(
        /*************************************************
        *  Resource + asic cap harcoding                *
        *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap.num_timing_generator;
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
index b7051bf..85af37c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
@@ -1240,7 +1240,7 @@ static bool dce112_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
index 7ee70f7..7d5c7da 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
@@ -1081,7 +1081,7 @@ static bool dce120_resource_construct(
        /* TODO: Fill more data from GreenlandAsicCapability.cpp */
        pool->base.pipe_count = res_cap.num_timing_generator;
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
 
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 8992772..fb18312 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -934,7 +934,7 @@ static bool dce80_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap.num_timing_generator;
        pool->base.timing_generator_count = res_cap.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
@@ -1137,7 +1137,7 @@ static bool dce81_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap_81.num_timing_generator;
        pool->base.timing_generator_count = res_cap_81.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
@@ -1337,7 +1337,7 @@ static bool dce83_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = res_cap_83.num_timing_generator;
        pool->base.timing_generator_count = res_cap_83.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 44178e9..cd4d703 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -1346,7 +1346,7 @@ static bool dcn10_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
 
        /* max pipe num for ASIC before check pipe fuses */
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index b50a250..5ba67e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -2429,7 +2429,7 @@ static bool dcn20_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
 
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index f7f7560..3a5dc8c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -1408,7 +1408,7 @@ static bool dcn21_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
 
        /* max pipe num for ASIC before check pipe fuses */
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 90223b7..8468c0f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -2297,7 +2297,7 @@ static bool dcn30_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index d21b928..0a110be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -1428,7 +1428,7 @@ static bool dcn301_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index d24b9b8..0b2fc84 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -1218,7 +1218,7 @@ static bool dcn302_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->pipe_count = pool->res_cap->num_timing_generator;
        pool->mpcc_count = pool->res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 0b44a33..a500013 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -1159,7 +1159,7 @@ static bool dcn303_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->pipe_count = pool->res_cap->num_timing_generator;
        pool->mpcc_count = pool->res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 428524f..55a11d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -1894,7 +1894,7 @@ static bool dcn31_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 795de8f..b74a167 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -1827,7 +1827,7 @@ static bool dcn314_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index 4db684f..d69c188 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -1866,7 +1866,7 @@ static bool dcn315_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
 
        /* Enable 4to1MPC by default */

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index db94141..c20521d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -1741,7 +1741,7 @@ static bool dcn316_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 2b9d8d2..3c0d046 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2191,7 +2191,7 @@ static bool dcn32_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.timing_generator_count = num_pipes;
        pool->base.pipe_count = num_pipes;
        pool->base.mpcc_count = num_pipes;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index e3dc4b1..b8ae6e8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1695,7 +1695,7 @@ static bool dcn321_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.timing_generator_count = num_pipes;
        pool->base.pipe_count = num_pipes;
        pool->base.mpcc_count = num_pipes;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 5118bec..f4a7510 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1850,7 +1850,7 @@ static bool dcn35_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index b64ad2d..bf8e83d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1823,7 +1823,7 @@ static bool dcn351_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index 1ad44fb..fec0911 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -1826,7 +1826,7 @@ static bool dcn36_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 491860c..dc0f0ab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1915,7 +1915,7 @@ static bool dcn401_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.timing_generator_count = num_pipes;
        pool->base.pipe_count = num_pipes;
        pool->base.mpcc_count = num_pipes;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 6328b3d..11b302c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1864,7 +1864,7 @@ static bool dcn42_resource_construct(
        /*************************************************
         *  Resource + asic cap harcoding                *
         *************************************************/
-       pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+       pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        pool->base.pipe_count = num_pipes;
        pool->base.mpcc_count = num_pipes;