drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates

In case of UHBR rates, we do not need to explicitly enable FEC by writing
to DP_TP_CTL register.
For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
setting fec_enable to false. However, it gets overwritten in
intel_dp_dsc_compute_config(). This change keeps fec_enable false across
MST and SST use-cases for UHBR rates.

While at it, add a comment explaining why we don't enable FEC in eDP v1.5.

v2: Correct logic to cater to SST use-cases (Jani)

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822061448.4085693-1-chaitanya.kumar.borah@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b1b512e..cb0f6db 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2310,9 +2310,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                &pipe_config->hw.adjusted_mode;
        int ret;
 
+       /*
+        * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
+        * Since, FEC is a bandwidth overhead, continue to not enable it for
+        * eDP. Until, there is a good reason to do so.
+        */
        pipe_config->fec_enable = pipe_config->fec_enable ||
                (!intel_dp_is_edp(intel_dp) &&
-                intel_dp_supports_fec(intel_dp, connector, pipe_config));
+                intel_dp_supports_fec(intel_dp, connector, pipe_config) &&
+                !intel_dp_is_uhbr(pipe_config));
 
        if (!intel_dp_supports_dsc(connector, pipe_config))
                return -EINVAL;