drm/amdgpu: drop BOOLEAN define in display part
authorFlora Cui <flora.cui@amd.com>
Tue, 8 Sep 2020 07:26:43 +0000 (15:26 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Sep 2020 21:52:40 +0000 (17:52 -0400)
use bool directly

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

index c5f2216..6a28fdd 100644 (file)
@@ -810,7 +810,7 @@ pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
 }
 
 static enum pp_smu_status pp_nv_set_pstate_handshake_support(
-       struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
+       struct pp_smu *pp, bool pstate_handshake_supported)
 {
        const struct dc_context *ctx = pp->dm;
        struct amdgpu_device *adev = ctx->driver_context;
index ae608c3..3586934 100644 (file)
@@ -30,8 +30,6 @@
  * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
  */
 
-typedef bool BOOLEAN;
-
 enum pp_smu_ver {
        /*
         * PP_SMU_INTERFACE_X should be interpreted as the interface defined
@@ -240,7 +238,7 @@ struct pp_smu_funcs_nv {
         * DC hardware
         */
        enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
-                       BOOLEAN pstate_handshake_supported);
+                       bool pstate_handshake_supported);
 };
 
 #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8