reg = <0x0 0x3160000 0x0 0x100>;
status = "disabled";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C1
&bpmp TEGRA234_CLK_PLLP_OUT0>;
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x3180000 0x0 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C3
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x3190000 0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C4
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x31b0000 0x0 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C6
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x31c0000 0x0 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C7
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x31e0000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C9
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0xc240000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C2
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0xc250000 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C8