return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
}
-static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static int clk_aic32x4_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
struct clk_aic32x4_pll_muldiv settings;
+ unsigned long rate;
int ret;
- ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
+ ret = clk_aic32x4_pll_calc_muldiv(&settings, req->rate, req->best_parent_rate);
if (ret < 0)
- return 0;
+ return -EINVAL;
- return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
+ rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate);
+ if (rate < 0)
+ return rate;
+
+ req->rate = rate;
+ return 0;
}
static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
.unprepare = clk_aic32x4_pll_unprepare,
.is_prepared = clk_aic32x4_pll_is_prepared,
.recalc_rate = clk_aic32x4_pll_recalc_rate,
- .round_rate = clk_aic32x4_pll_round_rate,
+ .determine_rate = clk_aic32x4_pll_determine_rate,
.set_rate = clk_aic32x4_pll_set_rate,
.set_parent = clk_aic32x4_pll_set_parent,
.get_parent = clk_aic32x4_pll_get_parent,