MIPS: Convert R10000_LLSC_WAR info a config option

Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5df92ae..87ef000 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -669,6 +669,7 @@ config SGI_IP27
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_NUMA
        select SYS_SUPPORTS_SMP
+       select WAR_R10000_LLSC
        select MIPS_L1_CACHE_SHIFT_7
        select NUMA
        help
@@ -704,6 +705,7 @@ config SGI_IP28
        select SYS_HAS_EARLY_PRINTK
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
+       select WAR_R10000_LLSC
        select MIPS_L1_CACHE_SHIFT_7
        help
          This is the SGI Indigo2 with R10000 processor.  To compile a Linux
@@ -730,6 +732,7 @@ config SGI_IP30
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_SMP
+       select WAR_R10000_LLSC
        select MIPS_L1_CACHE_SHIFT_7
        select ARC_MEMORY
        help
@@ -2675,6 +2678,11 @@ config WAR_TX49XX_ICACHE_INDEX_INV
 config WAR_ICACHE_REFILLS
        bool
 
+# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
+# may cause ll / sc and lld / scd sequences to execute non-atomically.
+config WAR_R10000_LLSC
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 2bf8f60..d852484 100644 (file)
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -21,7 +21,7 @@
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)             \
 {                                                                      \
-       if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
+       if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {       \
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
@@ -133,7 +133,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
        if (!access_ok(uaddr, sizeof(u32)))
                return -EFAULT;
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
                __asm__ __volatile__(
                "# futex_atomic_cmpxchg_inatomic                        \n"
                "       .set    push                                    \n"

diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h
index c49738b..ec09fe5 100644 (file)
--- a/arch/mips/include/asm/llsc.h
+++ b/arch/mips/include/asm/llsc.h
@@ -28,7 +28,7 @@
  * works around a bug present in R10000 CPUs prior to revision 3.0 that could
  * cause ll-sc sequences to execute non-atomically.
  */
-#if R10000_LLSC_WAR
+#ifdef CONFIG_WAR_R10000_LLSC
 # define __SC_BEQZ "beqzl      "
 #elif MIPS_ISA_REV >= 6
 # define __SC_BEQZ "beqzc      "

diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index fef0fda..ecda729 100644 (file)
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -31,7 +31,7 @@ static __inline__ long local_add_return(long i, local_t * l)
 {
        unsigned long result;
 
-       if (kernel_uses_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
                unsigned long temp;
 
                __asm__ __volatile__(
@@ -80,7 +80,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
 {
        unsigned long result;
 
-       if (kernel_uses_llsc && R10000_LLSC_WAR) {
+       if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
                unsigned long temp;
 
                __asm__ __volatile__(

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1061917..52be378 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR      \

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 966f40a..2229c83 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MACH_GENERIC_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 99f6531..f10efe5 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP22_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index d8dfa72..0a07cf6 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP27_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index f252df7..9fdc642 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP28_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 58ff9ca..8a8ec55 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,11 +7,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#ifdef CONFIG_CPU_R10000
-#define R10000_LLSC_WAR                        1
-#else
-#define R10000_LLSC_WAR                        0
-#endif
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ca3efe4..9e8c0c2 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_IP32_WAR_H */

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index b7827eb..76f7de2 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index b7827eb..76f7de2 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index fe04d05..dcb80b5 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_RM_WAR_H */

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7c376f6..0cf25ee 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 5768889..8e572d7 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index a094282..d405ecb 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,14 +93,6 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
- * may cause ll / sc and lld / scd sequences to execute non-atomically.
- */
-#ifndef R10000_LLSC_WAR
-#error Check setting of R10000_LLSC_WAR for your platform
-#endif
-
 /*
  * 34K core erratum: "Problems Executing the TLBR Instruction"
  */

diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index c333e57..2afa3ee 100644 (file)
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -106,7 +106,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
        if (unlikely(!access_ok((const void __user *)addr, 4)))
                return -EINVAL;
 
-       if (cpu_has_llsc && R10000_LLSC_WAR) {
+       if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
                __asm__ __volatile__ (
                "       .set    push                                    \n"
                "       .set    arch=r4000                              \n"

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 14f8ba9..e931eb0 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -90,7 +90,7 @@ static inline int __maybe_unused bcm1250_m3_war(void)
 
 static inline int __maybe_unused r10000_llsc_war(void)
 {
-       return R10000_LLSC_WAR;
+       return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
 }
 
 static int use_bbit_insns(void)