drm/i915/rkl: Disable PSR2
authorJosé Roberto de Souza <jose.souza@intel.com>
Wed, 3 Jun 2020 21:15:28 +0000 (14:15 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 4 Jun 2020 21:04:43 +0000 (14:04 -0700)
RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
tracking.  The driver is required to track the areas that needs update
and program hardware to send selective updates.

So until the software tracking is implemented, PSR2 needs to be disabled
for platforms without PSR2 HW tracking.

BSpec: 50422
BSpec: 50424

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200603211529.3005059-15-matthew.d.roper@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/intel_device_info.h

index b7a2c10..714c590 100644 (file)
@@ -646,6 +646,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
                return false;
        }
 
+       /*
+        * Some platforms lack PSR2 HW tracking and instead require manual
+        * tracking by software.  In this case, the driver is required to track
+        * the areas that need updates and program hardware to send selective
+        * updates.
+        *
+        * So until the software tracking is implemented, PSR2 needs to be
+        * disabled for platforms without PSR2 HW tracking.
+        */
+       if (!HAS_PSR_HW_TRACKING(dev_priv)) {
+               drm_dbg_kms(&dev_priv->drm,
+                           "No PSR2 HW tracking in the platform\n");
+               return false;
+       }
+
        /*
         * DSC and PSR2 cannot be enabled simultaneously. If a requested
         * resolution requires DSC to be enabled, priority is given to DSC
index 472f601..7a9ea43 100644 (file)
@@ -1643,6 +1643,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)               (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
 #define HAS_PSR(dev_priv)               (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR_HW_TRACKING(dev_priv) \
+       (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_TRANSCODER(dev_priv, trans)         ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6)
index 54b258a..8d0212d 100644 (file)
@@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
        .display.has_ddi = 1, \
        .has_fpga_dbg = 1, \
        .display.has_psr = 1, \
+       .display.has_psr_hw_tracking = 1, \
        .display.has_dp_mst = 1, \
        .has_rc6p = 0 /* RC6p removed-by HSW */, \
        HSW_PIPE_OFFSETS, \
@@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = {
        .display.has_fbc = 1, \
        .display.has_hdcp = 1, \
        .display.has_psr = 1, \
+       .display.has_psr_hw_tracking = 1, \
        .has_runtime_pm = 1, \
        .display.has_csr = 1, \
        .has_rc6 = 1, \
@@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = {
        .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                BIT(TRANSCODER_C),
        .require_force_probe = 1,
+       .display.has_psr_hw_tracking = 0,
        .engine_mask =
                BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
index 3613c04..34dbffd 100644 (file)
@@ -148,6 +148,7 @@ enum intel_ppgtt_type {
        func(has_modular_fia); \
        func(has_overlay); \
        func(has_psr); \
+       func(has_psr_hw_tracking); \
        func(overlay_needs_physical); \
        func(supports_tv);