drm/amdgpu/discovery: add a function to get the mall_size
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 29 Mar 2022 21:23:49 +0000 (17:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Apr 2022 21:47:30 +0000 (17:47 -0400)
Add a function to fetch the mall size from the IP discovery
table. Properly handle harvest configurations where more
or less cache may be available.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h

index c16239e..402e125 100644 (file)
@@ -1250,6 +1250,52 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
        return 0;
 }
 
+union mall_info {
+       struct mall_info_v1_0 v1;
+};
+
+int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
+{
+       struct binary_header *bhdr;
+       union mall_info *mall_info;
+       u32 u, mall_size_per_umc, m_s_present, half_use;
+       u64 mall_size;
+
+       if (!adev->mman.discovery_bin) {
+               DRM_ERROR("ip discovery uninitialized\n");
+               return -EINVAL;
+       }
+
+       bhdr = (struct binary_header *)adev->mman.discovery_bin;
+       mall_info = (union mall_info *)(adev->mman.discovery_bin +
+                       le16_to_cpu(bhdr->table_list[MALL_INFO].offset));
+
+       switch (le16_to_cpu(mall_info->v1.header.version_major)) {
+       case 1:
+               mall_size = 0;
+               mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
+               m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
+               half_use = le32_to_cpu(mall_info->v1.m_half_use);
+               for (u = 0; u < adev->gmc.num_umc; u++) {
+                       if (m_s_present & (1 << u))
+                               mall_size += mall_size_per_umc * 2;
+                       else if (half_use & (1 << u))
+                               mall_size += mall_size_per_umc / 2;
+                       else
+                               mall_size += mall_size_per_umc;
+               }
+               adev->gmc.mall_size = mall_size;
+               break;
+       default:
+               dev_err(adev->dev,
+                       "Unhandled MALL info table %d.%d\n",
+                       le16_to_cpu(mall_info->v1.header.version_major),
+                       le16_to_cpu(mall_info->v1.header.version_minor));
+               return -EINVAL;
+       }
+       return 0;
+}
+
 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
 {
        /* what IP to use for this? */
index 14537ce..752fb2e 100644 (file)
@@ -34,6 +34,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
                                     int *major, int *minor, int *revision);
 
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
+int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev);
 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev);
 
 #endif /* __AMDGPU_DISCOVERY__ */