ARM: dts: berlin: add PPI cpu mask to twd timer interrupts
authorJisheng Zhang <jszhang@marvell.com>
Fri, 26 Dec 2014 08:58:00 +0000 (16:58 +0800)
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Wed, 7 Jan 2015 14:25:37 +0000 (15:25 +0100)
According to the gic binding document, "bits[15:8] PPI interrupt cpu
mask.  Each bit corresponds to each of the 8 possible cpus attached to
the GIC.  A bit set to '1' indicated the interrupt is wired to that
CPU." This patch wants to add the PPI cpu mask for completeness.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
arch/arm/boot/dts/berlin2.dtsi
arch/arm/boot/dts/berlin2cd.dtsi
arch/arm/boot/dts/berlin2q.dtsi

index 015a06c..63d00a6 100644 (file)
                local-timer@ad0600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
-                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&chip CLKID_TWD>;
                };
 
index a318bc3..81b670a 100644 (file)
@@ -76,7 +76,7 @@
                local-timer@ad0600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
-                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&chip CLKID_TWD>;
                };
 
index 933dcbb..41a683f 100644 (file)
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
                        clocks = <&chip CLKID_TWD>;
-                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                };
 
                gic: interrupt-controller@ad1000 {