The i.MX SoCs have various clock configurations routed into the PCIe IP,
the list of clock is below. Document all those configurations in the DT
binding document.
All SoCs: pcie, pcie_bus
6QDL, 7D: + pcie_phy
6SX: + pcie_phy pcie_inbound_axi
8MQ: + pcie_phy pcie_aux
8MM, 8MP: + pcie_aux
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221211024859.672076-1-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
items:
- const: pcie
- const: pcie_bus
- - const: pcie_phy
+ - enum: [ pcie_phy, pcie_aux ]
- enum: [ pcie_inbound_axi, pcie_aux ]
num-lanes:
items:
- {}
- {}
- - {}
+ - const: pcie_phy
- const: pcie_inbound_axi
- if:
properties:
items:
- {}
- {}
- - {}
+ - const: pcie_phy
- const: pcie_aux
- if:
properties:
enum:
- fsl,imx6sx-pcie
- fsl,imx8mq-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ then:
+ properties:
+ clock-names:
+ maxItems: 3
+ contains:
+ const: pcie_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
then:
properties:
clock-names:
maxItems: 3
+ contains:
+ const: pcie_aux
unevaluatedProperties: false